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Wed, 13 Feb 2019 07:11:38 +0000 (GMT) Subject: Re: [PATCH 3/4] clk: samsung: exynos5410: Add gate clock for ADC To: Krzysztof Kozlowski , Rob Herring , Mark Rutland , Kukjin Kim , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org From: Chanwoo Choi Organization: Samsung Electronics Message-ID: Date: Wed, 13 Feb 2019 16:11:38 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190212175052.6310-4-krzk@kernel.org> Content-Language: en-US Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFJsWRmVeSWpSXmKPExsWy7bCmvq724eQYg747nBbzj5xjteh//JrZ 4vz5DewWmx5fY7X42HOP1eLyrjlsFjPO72OyWHr9IpPFxVOuFq17j7BbHH7Tzmrx79pGFotV u/4wOvB6rJm3htHj/Y1Wdo+ds+6ye2xa1cnmsXlJvUffllWMHp83yQWwR2XbZKQmpqQWKaTm JeenZOal2yp5B8c7x5uaGRjqGlpamCsp5CXmptoqufgE6Lpl5gAdq6RQlphTChQKSCwuVtK3 synKLy1JVcjILy6xVUotSMkpsCzQK07MLS7NS9dLzs+1MjQwMDIFKkzIzmh5upit4B1Hxfrd bg2Mm9i7GDk5JARMJLrPLmbuYuTiEBLYwSjRuX0yWEJI4BOjxKV/lhCJb4wSHyd3w3VcWPCK ESKxl1Hi+aVLbBDOe0aJrsVHWEGqhAU8JdrvnQCbKyJwk1niwOR+NpAEm4CWxP4XN8BsfgFF ias/HjOC2LwCdhKbLv5k6mLk4GARUJU43mkAEhYViJA43PsOqkRQ4uTMJywgNifQFV3TLjOB 2MwC4hK3nsyHsuUlmrfOBtsrITCPXeLSoSYmiLNdJJr73rBA2MISr45vgXpHSuJlfxuUXS2x 8uQRNojmDkaJLfsvsEIkjCX2L50MdhyzgKbE+l36EMv4JN597WEFCUsI8Ep0tAlBVCtLXH5w F2qtpMTi9k42CNtDonf5V0ZI8G5klOj/4jqBUWEWktdmIXlnFpJ3ZiEsXsDIsopRLLWgODc9 tdiwwBg5sjcxgtOxlvkOxg3nfA4xCnAwKvHwrjiaFCPEmlhWXJl7iFGCg1lJhDd+Y3KMEG9K YmVValF+fFFpTmrxIUZTYMBPZJYSTc4H5oq8knhDUyNjY2MLE0MzU0NDJXHe9Q7OMUIC6Ykl qdmpqQWpRTB9TBycUg2ME65LdvauF/S2f54av3drualaq+Irbb8NnN5Nrofvnj16JsX+2uVU xo+KUQyM8XOaz2f2+wmrfHE8GtJ1U23+h4yPCZsrbG5cd389kz/l14HznHsV9+iuyGcUjFro 8tkv+dqve3N2/LkmXHK1tmd+vEfJLN/7+Q4LNueW7a5csYHddHe818NwJZbijERDLeai4kQA x97/It0DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRmVeSWpSXmKPExsWy7bCSvK7W4eQYgxfPNS3mHznHatH/+DWz xfnzG9gtNj2+xmrxseceq8XlXXPYLGac38dksfT6RSaLi6dcLVr3HmG3OPymndXi37WNLBar dv1hdOD1WDNvDaPH+xut7B47Z91l99i0qpPNY/OSeo++LasYPT5vkgtgj+KySUnNySxLLdK3 S+DKaHm6mK3gHUfF+t1uDYyb2LsYOTkkBEwkLix4xQhiCwnsZpRY06YDEZeUmHbxKHMXIweQ LSxx+HBxFyMXUMlbRokl12+xgtQIC3hKtN87wQySEBG4zSyx9FUbO0TVRkaJbV9usYFUsQlo Sex/cQPM5hdQlLj64zHYNl4BO4lNF38ygWxgEVCVON5pABIWFYiQ+Ph0HxNEiaDEyZlPWEBs TqBDu6ZdBoszC6hL/Jl3iRnCFpe49WQ+VFxeonnrbOYJjEKzkLTPQtIyC0nLLCQtCxhZVjFK phYU56bnFhsWGOallusVJ+YWl+al6yXn525iBMefluYOxstL4g8xCnAwKvHwrjiaFCPEmlhW XJl7iFGCg1lJhDd+Y3KMEG9KYmVValF+fFFpTmrxIUZpDhYlcd6neccihQTSE0tSs1NTC1KL YLJMHJxSDYwt/1PO319zweyV1tbpyyaohZ532usgMeWk7GS9isJb29ZMVJq9XOPWSsb8fzaB 715GHZ03/6z+o464WzPuxt36v71ur7Ks1YG5C8vsPcPPPm1ZUv2md91ckQXzfLL5/z4+6LvH 4PSy1kK+m188/7/jSdX9fGVnsBLvUQtTkd6vYUaroqQ2WJ7PV2Ipzkg01GIuKk4EABcR2Hy7 AgAA X-CMS-MailID: 20190213071138epcas1p1682f47f1d1be2992b9f4926cbce48f36 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20190212175212epcas5p4ff5ed8b2264956844e14d5e6ca03eac6 References: <20190212175052.6310-1-krzk@kernel.org> <20190212175052.6310-4-krzk@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote: > Add the gate clock for ADC block on Exynos5410. > > Signed-off-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos5410.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c > index 0a0b09591e6f..b2da2c8fa0c7 100644 > --- a/drivers/clk/samsung/clk-exynos5410.c > +++ b/drivers/clk/samsung/clk-exynos5410.c > @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { > GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), > GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), > GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), > + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), > GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), > > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", > I checked it on Exynos5410 TRM. Looks good to me. Acked-by: Chanwoo Choi -- Best Regards, Chanwoo Choi Samsung Electronics