From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2D2F261B9B for ; Sun, 10 May 2026 08:55:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778403360; cv=none; b=D5Hk+0CmB3vOXNfBT6PKLpCGI366Kx31TUuQD0VCZfxOLqcfEyzqhRvWbWY1sgU4UZsVgfs2P3tO1uisU09BkvtwViuvg+yxuz8MpLJFIVZl3P0Zxf+vzXVYypki89qK4MsnjnxcUxVJK25cxdKjNdrf73E7Dl9MQouoKQ7pj/0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778403360; c=relaxed/simple; bh=YwiW+Q760MzYPbYvu9d9Xiw/mH/fNOhKEvXvG0HvquM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=BhjkFhz4VRFs0/UT2i6KBpZ12fhm5THsVCh+Dt5w2m1Xc4pzu5igvVZP6VTGfbqPEKoIytOrAhpn4+0JQ6JqXKCsK0a9GuGCjVxcLCYz/Tu5a4uOE9uHO88pTwMnuqz+iTF+6IDx0RQiLn7R8ffG5r5sSk9m1vAVonZpp4/Yf90= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QFE5N1A3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QFE5N1A3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1778403351; bh=YwiW+Q760MzYPbYvu9d9Xiw/mH/fNOhKEvXvG0HvquM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=QFE5N1A3ga/Uu86j6mV7t3ln6mwZ1ZepXAvnVa8kVVlSGomKkqDfL4Dd8xoPkSgid RXCobStc/4gG8ymUdAmhwuEB1q2NlbHf3r1zmIFmdCsX47j1BvvyT4zNV8E9/p7ats LIt88bgCnLWvpv3zvTGpM3Y9QsngbCCkuA+/BkcPvdtP4FvdkvdvPz9IA/rjlNyfCC DlZuoEUMW0FnCzogFBS4Vh1tCfNjH5m6Qz73ywUdGDU29zP6194sCg5R4CdpUlydw4 sp7ITNzvHApAAk572rSvCT6mWEHj/CDaGeGpx1r7d1ENBUSCTw/BfYKtKSDNfuNxPS y7AV31Hxou9xg== Received: from [100.64.0.241] (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id B4AED17E0EB6; Sun, 10 May 2026 10:55:50 +0200 (CEST) Message-ID: Date: Sun, 10 May 2026 11:55:50 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups To: Vinod Koul Cc: Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com> Content-Language: en-US From: Cristian Ciocaltea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Vinod, On 5/10/26 10:36 AM, Vinod Koul wrote: > On 27-02-26, 22:48, Cristian Ciocaltea wrote: >> This series provides a set of bug fixes and cleanups for the Rockchip >> Samsung HDPTX PHY driver. >> >> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate >> calculation and synchronization issues. Specifically, it fixes edge >> cases where the PHY PLL is pre-programmed by an external component (like >> a bootloader) or when changing the color depth (bpc) while keeping the >> modeline constant. Because the Common Clock Framework .set_rate() >> callback might not be invoked if the pixel clock remains unchanged, this >> previously led to out-of-sync states between CCF and the actual HDMI PHY >> configuration. >> >> The second part focuses on code cleanups and modernizing the register >> access. Now that dw_hdmi_qp driver has fully switched to using >> phy_configure(), we can drop the deprecated TMDS rate setup workarounds >> and the restrict_rate_change flag logic. Finally, it refactors the >> driver to consistently use standard bitfield macros. > > Sorry looks like I have missed to review this one. > Can you please rebase on phy/fixes and send... I've just verified and it applies cleanly on top of phy/fixes. Do you still need a resend? Regards, Cristian