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DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; DKIM_TRACE(0.00)[suse.de:+] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org Hi Jim, On 8/1/24 01:28, Jim Quinlan wrote: > Provide support for new chips with multiple inbound windows while > keeping the legacy support for the older chips. > > In existing chips there are three inbound windows with fixed purposes: the > first was for mapping SoC internal registers, the second was for memory, > and the third was for memory but with the endian swapped. Typically, only > one window was used. > > Complicating the inbound window usage was the fact that the PCIe HW would > do a baroque internal mapping of system memory, and concatenate the regions > of multiple memory controllers. > > Newer chips such as the 7712 and Cable Modem SOCs take a step forward and > drop the internal mapping while providing for multiple inbound windows. > This works in concert with the dma-ranges property, where each provided > range becomes an inbound window. > > Signed-off-by: Jim Quinlan > --- > drivers/pci/controller/pcie-brcmstb.c | 228 ++++++++++++++++++++------ > 1 file changed, 177 insertions(+), 51 deletions(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 4659208ae8da..0ecca3d9576f 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -75,15 +75,19 @@ > #define PCIE_MEM_WIN0_HI(win) \ > PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8) > > +/* > + * NOTE: You may see the term "BAR" in a number of register names used by > + * this driver. The term is an artifact of when the HW core was an > + * endpoint device (EP). Now it is a root complex (RC) and anywhere a > + * register has the term "BAR" it is related to an inbound window. > + */ > + > +#define PCIE_BRCM_MAX_INBOUND_WINS 16 > #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c > #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f > > -#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 > -#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f > -#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 > +#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4 > > -#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c > -#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f > > #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044 > #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048 > @@ -130,6 +134,10 @@ > (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ > PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) > > +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac > +#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK BIT(0) > +#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP 0x410c > + > #define PCIE_MSI_INTR2_BASE 0x4500 > > /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */ > @@ -217,12 +225,20 @@ enum pcie_type { > BCM4908, > BCM7278, > BCM2711, > + BCM7712, > +}; > + > +struct inbound_win { > + u64 size; > + u64 pci_offset; > + u64 cpu_addr; > }; > > struct pcie_cfg_data { > const int *offsets; > const enum pcie_type type; > const bool has_phy; > + unsigned int num_inbound_wins; > void (*perst_set)(struct brcm_pcie *pcie, u32 val); > void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); > }; > @@ -274,6 +290,7 @@ struct brcm_pcie { > struct subdev_regulators *sr; > bool ep_wakeup_capable; > bool has_phy; > + int num_inbound_wins; Could you unify the type of num_inbound_wins field. I think u8 should be enough? > }; > > static inline bool is_bmips(const struct brcm_pcie *pcie) > @@ -789,23 +806,61 @@ static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) > writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); > } > > -static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, > - u64 *rc_bar2_size, > - u64 *rc_bar2_offset) > +static inline void set_bar(struct inbound_win *b, int *count, u64 size, The number of BARs cannot be more than 256, could you make "count" an u8 like the num_inbound_wins. > + u64 cpu_addr, u64 pci_offset) > +{ > + b->size = size; > + b->cpu_addr = cpu_addr; > + b->pci_offset = pci_offset; > + (*count)++; > +} > + In case you send a new version please address the comments, otherwise Reviewed-by: Stanimir Varbanov ~Stan