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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b48652a9ea1sm1633510466b.16.2025.10.08.05.30.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 05:30:14 -0700 (PDT) Message-ID: Date: Wed, 8 Oct 2025 14:30:12 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/9] arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support To: Md Sadre Alam , broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, vkoul@kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: quic_varada@quicinc.com References: <20251008090413.458791-1-quic_mdalam@quicinc.com> <20251008090413.458791-5-quic_mdalam@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251008090413.458791-5-quic_mdalam@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA3MDE0NiBTYWx0ZWRfX+LR/RWOQSfnQ +9EYTPTI1OpiAtj28wvibpT1nbiseQjNObzT6+zPFPadsgPnXqqXwvlFTQ7mqLTFbc8LxMfSX5y DoiU4BHSwYIxboYXR7btBa+s8yRFzo8sP94x+4KjbTlg7t0D4rHH899jILkMOZNgWoxlG+fnpyv ze0Bwi0i8yIWi9p07KOnOFmkfWMZj7mqDKYROjQdpJrTIKyF1zmqujSHw82dINxbu4h5xVFDhoA xpihAaVpzKa6T/+BNv6nWcu6Bi66QnT7N9xrK38d8qK01MIcPoPR9HEeyXMV2JLkYRg/pjr9Ku5 wVgDk+PAHGr8qjiD/WRDAgNvv5biXuo2QegAh5wXdJa8ccmjWrSLsx3lGXLksEw2luw6w0R1gJQ 5+0+3TKUmRQTGE2J/dqzuLponY709g== X-Proofpoint-ORIG-GUID: ZRGeFkzL1x0Bsmz8i6rOZGNvIuxjBfis X-Proofpoint-GUID: ZRGeFkzL1x0Bsmz8i6rOZGNvIuxjBfis X-Authority-Analysis: v=2.4 cv=cKbtc1eN c=1 sm=1 tr=0 ts=68e65959 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=COk6AnOGAAAA:8 a=-ept-RJRzOG-hoP0ccsA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_04,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510070146 On 10/8/25 11:04 AM, Md Sadre Alam wrote: > Add device tree nodes for QPIC SPI NAND flash controller support > on IPQ5424 SoC. > > The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash > devices with hardware ECC capabilities and DMA support through BAM > (Bus Access Manager). > > Signed-off-by: Md Sadre Alam > --- [...] > + qpic_bam: dma-controller@7984000 { > + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; > + reg = <0x0 0x07984000 0x0 0x1c000>; > + interrupts = ; > + clocks = <&gcc GCC_QPIC_AHB_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + status = "disabled"; > + }; > + > + qpic_nand: spi@79b0000 { > + compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand"; > + reg = <0x0 0x079b0000 0x0 0x10000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QPIC_CLK>, > + <&gcc GCC_QPIC_AHB_CLK>, > + <&gcc GCC_QPIC_IO_MACRO_CLK>; > + clock-names = "core", "aon", "iom"; 1 a line, please, also below > + dmas = <&qpic_bam 0>, > + <&qpic_bam 1>, > + <&qpic_bam 2>; > + dma-names = "tx", "rx", "cmd"; > + status = "disabled"; Is there anything preventing us from enabling both these nodes by default on all boards (maybe secure configuration or required regulators)? Konrad