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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2be08817bsm1696312e87.27.2026.07.27.12.21.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jul 2026 12:21:29 -0700 (PDT) Message-ID: Date: Mon, 27 Jul 2026 22:21:28 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] i2c: qcom-cci: Switch msm8953 to the CCI v2 timing/rate config To: Loic Poulain , Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260727-cci-clk-fix-v2-0-c3958f28b045@oss.qualcomm.com> <20260727-cci-clk-fix-v2-1-c3958f28b045@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20260727-cci-clk-fix-v2-1-c3958f28b045@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Loic, On 7/27/26 12:21, Loic Poulain wrote: > The msm8953 CCI timing table is internally inconsistent. Its Standard likely I was misunderstood in my v1 review comments, and I believe v3 will be needed... If there is just one master, or two masters set in equal speed mode, then there is no such issue as "msm8953 CCI timing table is internally inconsistent". In other words generally it shall be permitted to have supply clock frequency intermixed speed modes for any CCI variant. I'll repeat the same point as given in v1, namely supply clock frequency is not a property of CCI revision (therefore v1 1/3 or v2 2/3 is invalid), it is a property of the mode settings. It's correct to remove 'cci_clk_rate' from 'struct cci_data', and it will be correct to add (or parameterize in any other way) 'cci_clk_rate' to 'struct hw_params'. Each instance of 'struct hw_params' is strictly bound to a particular CCI clock frequency. > and Fast timings match v1/v1.5, which are calibrated for a 19.2 MHz CCI > clock, but its Fast+ timings are essentially the v2 values, which are > calibrated for 37.5 MHz. Since all masters share a single CCI clock, But what if you have only one master?.. I think the msm8953 data is correct, it shall not be removed. > no single rate can satisfy all three modes with the current table, and > the DT assigns 19.2 MHz, so Fast+ timings are wrong. They are not wrong, eh... > > The msm8953 CCI is the same hardware version as msm8996/sdm630, which > already use the cci_v2_data config (37.5 MHz). 37.5 MHz is supported by > the msm8953 CCI RCG, so reuse cci_v2_data for msm8953 as well and drop > the redundant, inconsistent standalone table. This makes all three I2C > modes self-consistent under a single clock rate. > > Note this requires the CCI clock to run at 37.5 MHz, the proper clock > rate will be set in an upcoming CCI patch. > > Signed-off-by: Loic Poulain -- Best wishes, Vladimir