From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD7B8C433F5 for ; Tue, 26 Apr 2022 06:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239010AbiDZGzL (ORCPT ); Tue, 26 Apr 2022 02:55:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229838AbiDZGzJ (ORCPT ); Tue, 26 Apr 2022 02:55:09 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAF8F31DDE; Mon, 25 Apr 2022 23:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650955922; x=1682491922; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=7N+AkLZICdgvisk/KZV8bky8vfCRSJNl9xIZ2mypSW8=; b=UEPlNMhJNFSsZ5WN6Ut0RQi1ZMpNVa3ow5qDmcm4/C0D7YjWfVkoeUY8 7PViwJbDF19S9wKY0nash9lMiTG7K/nOSUDjzLMUI2Se7yhT1IT4m3V5b FGLlqWgPF/7VV46StpBmnuTWYalZHoi+ZzvB0h3WFqXQN8Ggn8gVno69r l9bpc0ScrtKS8nLrWU8NnMp6I5Tkwdvx/ItVCOLf1s+2EANu8e2GsFHV0 LO9PSM+hkucaiyGO4yaTszmjr3SuUA5ilbbJzUjcMbm8KisCN9tbgXO7n 5hATppTkGvUprQ/deuNCNMr1PccZ6DBcAx+83nusPrdz3vAzoYEglDkL2 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10328"; a="263068459" X-IronPort-AV: E=Sophos;i="5.90,290,1643702400"; d="scan'208";a="263068459" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2022 23:52:02 -0700 X-IronPort-AV: E=Sophos;i="5.90,290,1643702400"; d="scan'208";a="558145715" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.252.58.98]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2022 23:51:56 -0700 Message-ID: Date: Tue, 26 Apr 2022 09:51:52 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Firefox/91.0 Thunderbird/91.7.0 Subject: Re: [PATCH V2 03/11] perf/x86: Add support for TSC in nanoseconds as a perf event clock Content-Language: en-US To: Thomas Gleixner , Peter Zijlstra Cc: Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , "linux-kernel@vger.kernel.org" , Ingo Molnar , Borislav Petkov , Dave Hansen , "x86@kernel.org" , "kvm@vger.kernel.org" , H Peter Anvin , Mathieu Poirier , Suzuki K Poulose , Leo Yan , "jgross@suse.com" , "sdeep@vmware.com" , "pv-drivers@vmware.com" , "pbonzini@redhat.com" , "seanjc@google.com" , "kys@microsoft.com" , "sthemmin@microsoft.com" , "virtualization@lists.linux-foundation.org" , "Andrew.Cooper3@citrix.com" , "Hall, Christopher S" References: <20220214110914.268126-1-adrian.hunter@intel.com> <20220214110914.268126-4-adrian.hunter@intel.com> <853ce127-25f0-d0fe-1d8f-0b0dd4f3ce71@intel.com> <30383f92-59cb-2875-1e1b-ff1a0eacd235@intel.com> <013b5425-2a60-e4d4-b846-444a576f2b28@intel.com> <6f07a7d4e1ad4440bf6c502c8cb6c2ed@intel.com> <50fd2671-6070-0eba-ea68-9df9b79ccac3@intel.com> <87ilqx33vk.ffs@tglx> <87fsm114ax.ffs@tglx> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <87fsm114ax.ffs@tglx> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/04/22 20:05, Thomas Gleixner wrote: > On Mon, Apr 25 2022 at 16:15, Adrian Hunter wrote: >> On 25/04/22 12:32, Thomas Gleixner wrote: >>> It's hillarious, that we still cling to this pvclock abomination, while >>> we happily expose TSC deadline timer to the guest. TSC virt scaling was >>> implemented in hardware for a reason. >> >> So you are talking about changing VMX TCS Offset on every VM-Entry to try to hide >> the time jumps when the VM is scheduled out? Or neglect that and just let the time >> jumps happen? >> >> If changing VMX TCS Offset, how can TSC be kept consistent between each VCPU i.e. >> wouldn't that mean each VCPU has to have the same VMX TSC Offset? > > Obviously so. That's the only thing which makes sense, no? [ Sending this again, because I notice I messed up the email "From" ] But wouldn't that mean changing all the VCPUs VMX TSC Offset at the same time, which means when none are currently executing? How could that be done?