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That inconsistency went unnoticed because > nova-core only ever uses the first register of each array at the moment. > > Signed-off-by: Alexandre Courbot > --- > drivers/gpu/nova-core/regs.rs | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) Reviewed-by: John Hubbard thanks, -- John Hubbard > > diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs > index 88662da634dc..df2eddc58efb 100644 > --- a/drivers/gpu/nova-core/regs.rs > +++ b/drivers/gpu/nova-core/regs.rs > @@ -402,19 +402,19 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { > register! { > base: NovaRegisters; > > - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { > + pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8, stride = 8] @ 0x008f2c00 { > 31:0 address => u32; > } > > - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { > + pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8, stride = 8] @ 0x008f2c04 { > 31:0 address => u32; > } > > - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { > + pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8, stride = 8] @ 0x008f2c80 { > 31:0 val => u32; > } > > - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { > + pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8, stride = 8] @ 0x008f2c84 { > 31:0 val => u32; > } > } >