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Thu, 23 Oct 2025 03:18:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHTvHNcr2Q4NEwC8d4MLm5CmnKWQFx1aJoWBr0IhgqiAMI6t5IKZWuVUChlyP0voh0nbGgtMg== X-Received: by 2002:a17:903:8c8:b0:277:c230:bfca with SMTP id d9443c01a7336-292d3e57324mr66629485ad.4.1761214703961; Thu, 23 Oct 2025 03:18:23 -0700 (PDT) Received: from [10.217.216.168] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2946de10b53sm18460375ad.23.2025.10.23.03.18.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 03:18:23 -0700 (PDT) Message-ID: Date: Thu, 23 Oct 2025 15:48:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 2/3] arm64: dts: qcom: sm8750: Add SDC2 nodes for sm8750 soc To: Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20251007054445.4096630-1-sarthak.garg@oss.qualcomm.com> <20251007054445.4096630-3-sarthak.garg@oss.qualcomm.com> Content-Language: en-US From: Sarthak Garg In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: mrsDFVQDdeqbFJsciWrdV_A7ThKE79qL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAzMSBTYWx0ZWRfX9iYefWIP3uJ0 ZyeQQcAZYgDMGYjO91zNDJTfFvAxzF/VKl3YxPvfc/N9QL5x2Y/IArkyVY0jy84LG6/fQnvYeGX tJbbPDQVsYcvPRyPOFSHACE2751BszHy67HNWwyj3/Wv2iKUFjKvIitvMUW8CDgm/xFwVjT9Td+ /kaz0jHGcPbdox954PlJH/v8beiF5Ub6YMA+eRsZBM3EARZMJvhaZdb5eBh9U484Yh+krRjKSWM tLJ1girHrRJkX8kH8OttjVWxGB1U6uHLECL5vyVE4In1yVv9YpPS+Jjooy6/iGkiiCUwo/sWVgU Q1HhiqWr7g2x/IxVziCre/72pAijsTAGxBojPwmOcyUlLA59U5rs31QcVoa/hw3UJz/296MUNXS XvKXR8D29+PmRmzeB+4k0gsP5nOLUQ== X-Authority-Analysis: v=2.4 cv=QYNrf8bv c=1 sm=1 tr=0 ts=68fa00f1 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=DMDGrHW2khae0FuLqQAA:9 a=hK1Zo0tywebNB7qn:21 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: mrsDFVQDdeqbFJsciWrdV_A7ThKE79qL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_08,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180031 On 10/8/2025 5:47 PM, Konrad Dybcio wrote: > On 10/7/25 7:44 AM, Sarthak Garg wrote: >> Add SD Card host controller for sm8750 soc. >> >> Signed-off-by: Sarthak Garg >> --- > [...] > >> + sdhc_2: mmc@8804000 { >> + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0 0x08804000 0 0x1000>; >> + >> + interrupts = , >> + ; >> + interrupt-names = "hc_irq", "pwr_irq"; > One a line, please Sure will update it in V2. >> + >> + clocks = <&gcc GCC_SDCC2_AHB_CLK>, >> + <&gcc GCC_SDCC2_APPS_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; > Please align the '<'s Sure will update it in V2. >> + clock-names = "iface", "core", "xo"; > One a line, please Sure will update it in V2. >> + >> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > and here Sure will update it in V2. > >> + >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + operating-points-v2 = <&sdhc2_opp_table>; >> + >> + qcom,dll-config = <0x0007442c>; >> + qcom,ddr-config = <0x80040868>; >> + >> + iommus = <&apps_smmu 0x540 0x0>; >> + dma-coherent; >> + >> + bus-width = <4>; >> + max-sd-hs-hz = <37500000>; >> + >> + resets = <&gcc GCC_SDCC2_BCR>; >> + status = "disabled"; > A \n before 'status' is customary Sure will update it in V2. > >> + >> + sdhc2_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-202000000 { >> + opp-hz = /bits/ 64 <202000000>; >> + required-opps = <&rpmhpd_opp_nom>; > This can work at SVS_L1 > > Konrad Sure will update to rpmhpd_opp_svs_l1 in V2. Regards, Sarthak