RE: [PATCH net-next] net: lan966x: Improve the CPU TX bitrate.

[David Laight <David.Laight@ACULAB.COM>]

From: Horatiu Vultur
> Sent: 08 March 2022 22:30
> 
> The 03/08/2022 22:36, Andrew Lunn wrote:
> >
> > >  static int lan966x_port_inj_ready(struct lan966x *lan966x, u8 grp)
> > >  {
> > > -     u32 val;
> > > +     unsigned long time = jiffies + usecs_to_jiffies(READL_TIMEOUT_US);
> > > +     int ret = 0;
> > >
> > > -     return readx_poll_timeout_atomic(lan966x_port_inj_status, lan966x, val,
> > > -                                      QS_INJ_STATUS_FIFO_RDY_GET(val) & BIT(grp),
> > > -                                      READL_SLEEP_US, READL_TIMEOUT_US);
> > > +     while (!(lan_rd(lan966x, QS_INJ_STATUS) &
> > > +              QS_INJ_STATUS_FIFO_RDY_SET(BIT(grp)))) {
> > > +             if (time_after(jiffies, time)) {
> > > +                     ret = -ETIMEDOUT;
> > > +                     break;
> > > +             }
> >
> > Did you try setting READL_SLEEP_US to 0? readx_poll_timeout_atomic()
> > explicitly supports that.
> 
> I have tried but it didn't improve. It was the same as before.

How many times round the loop is it going ?

It might be that by the time readx_poll_timeout_atomic()
gets around to reading the register the fifo is actually ready.

The there is the delay between detecting 'ready' and writing
the next data.
That delay might be cumulative and affect performance.

OTOH spinning waiting for fifo space is just plain horrid.
Reminds me of 3C509 drivers :-)

	David

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