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Mon, 26 Oct 2026 02:11:51 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b4459711d2sm3281710a12.17.2026.10.26.02.11.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 02:11:50 -0700 (PDT) Message-ID: Date: Mon, 26 Oct 2026 10:11:48 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/10] drm/msm/mdp5: flush the interface before starting the timing engine To: Dmitry Baryshkov , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Kalyan Thota , Federico Amedeo Izzo , Helen Koike , Vignesh Raman , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20261024-fd-kms-fix-smmu-v5-0-a5b0b284aead@oss.qualcomm.com> <20261024-fd-kms-fix-smmu-v5-4-a5b0b284aead@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261024-fd-kms-fix-smmu-v5-4-a5b0b284aead@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDAzNiBTYWx0ZWRfXxmHzOfLIWrn0 XZCqjEiwVMt1N+TCs0Vy1eCki0K5btlXkyeB4hWfROO2vSaTvflCRuJYRBzQyXHQ5TyLcz++90E 07MYPFFW7Cc99qFlXdbiSQtH6a25466o250z0Ak38CEuv2NeWoPtkzR5g1vYRHmuvFRn6trIcjf yqOW9dmJmWKFA7YLTJvajqWseW2xe7ovjS45GfsqCLwmiKY7rQZmYmjaoP+R0KdyA9uIHgc90bQ dn8cNXMlL1QKzvsRe9uuBv0bYOLLeg94teviMFiTY65147QugP2WAUiq6eKTBpoLau9+h6ZfINb 7N63G2NrZ6LHc+f+LTvVGFQ1v4fgzR62VTIqs/qJeN3JE4aaZj+aMksxSCgcyLFNegERT5hLU1L WOUy9Ou5cs53bip3QZA33IoBzrxNdHmk6TrqUeqhopje8bspzBlHViDxsnPN7b9Tfx3kscFhEb1 hqV+yleWHFu2P5jSbQg== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDAzNiBTYWx0ZWRfX2+eU7DkoFgBJ +vm1AFtoW1Di3zs8jr/jJ6uhLIp4K8RtnijxIY6jUyQGnrG+nCCk/mOQco1xfo2txQOrbbcbHs+ grSVPWa40u+yOBO9BghoApoayekx5qA= X-Proofpoint-ORIG-GUID: 6iZa3zpzZIlu17aIV8pvzwcP9LataAQq X-Authority-Analysis: v=2.4 cv=e+aT2qp/ c=1 sm=1 tr=0 ts=6adf1959 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=t3vDU1A9I6D9DDbkPvEA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: 6iZa3zpzZIlu17aIV8pvzwcP9LataAQq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610260036 On 10/24/26 1:25 AM, Dmitry Baryshkov wrote: > Disabling a CRTC and then enabling it again can produce an SMMU fault on > MSM8996 as soon as the timing engine restarts, e.g. when fbcon takes over > after kms_atomic: > > arm-smmu d00000.iommu: Unhandled context fault: fsr=0x402, iova=0x01fa6e00 > > The faulting address is inside the framebuffer that was scanned out > before the disable, which has been released since. The pipes keep that > address latched (CURRENT_SRC0_ADDR still points to the released buffer) > because the plane removal flushed after the timing engine stopped never > takes effect. On the next enable the pipes are programmed and flushed > before the encoder is enabled, but that flush doesn't include the > interface: the encoder enables the timing engine first and only then > flushes the INTF. The first frame is fetched with the latched pipe > configuration, from the released buffer. > > Flush the interface before enabling the timing engine, the order used by > both the DPU driver and the downstream mdss driver. With the INTF flush > pending, the whole pending flush takes effect when the timing engine > starts and the first frame is fetched with the new configuration. > > Fixes: 06c0dd96bfbb ("drm/msm: add mdp5/apq8x74") > Assisted-by: LLM > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad