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	id 1rgBUf-009B2N-CJ; Fri, 01 Mar 2024 23:36:41 +0100
Date: Fri, 1 Mar 2024 23:36:41 +0100
From: Andrew Lunn <andrew@lunn.ch>
To: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
Cc: joel@jms.id.au, andrew@aj.id.au, devicetree@vger.kernel.org,
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	robh+dt@kernel.org
Subject: Re: [PATCH v2 1/1] ARM:dts:aspeed: Initial device tree for AMD Onyx
 Platform
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References: <20240301222257.3309541-1-supreeth.venkatesh@amd.com>
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> +&mdio0 {
> +	status = "okay";
> +	ethphy0: ethernet-phy@0 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <0>;
> +	};
> +};
> +
> +&mac3 {
> +	status = "okay";
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_rgmii4_default>;
> +};

That looks odd. Where are the RGMII delays coming from? Normally its
"rgmii-id", which asks the PHY to insert the delays.

	Andrew