From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B24C4167D for ; Thu, 2 Nov 2023 12:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234817AbjKBMRM (ORCPT ); Thu, 2 Nov 2023 08:17:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347353AbjKBMQv (ORCPT ); Thu, 2 Nov 2023 08:16:51 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6657AD40; Thu, 2 Nov 2023 05:16:47 -0700 (PDT) Received: from kwepemm000007.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SLjTH6PLjzrTvq; Thu, 2 Nov 2023 20:13:39 +0800 (CST) Received: from [10.67.120.192] (10.67.120.192) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Thu, 2 Nov 2023 20:16:42 +0800 Message-ID: Date: Thu, 2 Nov 2023 20:16:42 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , Subject: Re: [PATCH net 6/7] net: hns3: fix VF reset fail issue To: Paolo Abeni , , , , , References: <20231028025917.314305-1-shaojijie@huawei.com> <20231028025917.314305-7-shaojijie@huawei.com> <9bc9514044063bc57155fb786f970ca1d69758b4.camel@redhat.com> From: Jijie Shao In-Reply-To: <9bc9514044063bc57155fb786f970ca1d69758b4.camel@redhat.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.120.192] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemm000007.china.huawei.com (7.193.23.189) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org on 2023/11/2 18:45, Paolo Abeni wrote: > On Sat, 2023-10-28 at 10:59 +0800, Jijie Shao wrote: >> >> -static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr) >> +static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr, >> + bool need_dalay) >> { >> +#define HCLGEVF_RESET_DELAY 5 >> + >> + if (need_dalay) >> + mdelay(HCLGEVF_RESET_DELAY); > 5ms delay in an interrupt handler is quite a lot. What about scheduling > a timer from the IH to clear the register when such delay is needed? > > Thanks! > > Paolo Using timer in this case will complicate the code and make maintenance difficult. We consider reducing the delay time by polling. For example, the code cycles every 50 us to check whether the write register takes effect. If yes, the function returns immediately. or the code cycles until 5 ms. Is this method appropriate? Thanks! Jijie