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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942f15d56fsm490516866b.56.2026.03.10.06.36.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 06:36:05 -0700 (PDT) Message-ID: Date: Tue, 10 Mar 2026 14:36:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi To: Krzysztof Kozlowski , Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski References: <20260224-eliza-base-dt-v1-0-54e8e3a5fe43@oss.qualcomm.com> <20260224-eliza-base-dt-v1-2-54e8e3a5fe43@oss.qualcomm.com> <521fcb9d-6538-430a-910e-0e4e9df2c693@oss.qualcomm.com> <1e58955c-3e79-4503-8670-85e689bf8acb@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <1e58955c-3e79-4503-8670-85e689bf8acb@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDExOCBTYWx0ZWRfXxk31Rqty1OLQ EDN408hzHFoDlJGr5CnL8Q+aFkK3Tp/2IH7qVeo3e+tR62C54wcizb5rY2JVqoVtJa6eiajJqwV v6rghAHREkVLiOVYSi2tD1frUtF/dIbR6PNeTh5YGLhMkPmsPetHfYsTra2Y5e108QRziNK1Aul 2QNiAlHSbG2E1JOE/pCrX8CIpVFGf5hxbfihJ+eHTVQzICU19p8+KGK1KKx3KwCV2o6WjvfuniN LzB+F+h6IvYPibpANn0Zg9vmf7Lcik/ew8YQjqSQnHDU3uPukohiBOD9nAS5he+U07e3iefX56V MYkyJNTwzBPF/HjvKBMcZspZg3vbEqatX6ctVu/lVpR3XSlmaslu/RRfrykCcQf/a6U5gBSoFq9 u9jgekIGK/EIKWIb2PxFV4Re4wq/G3q7jeDG/wVA8ysPfFL/MLEv5vKEFSfaqV05iV4iqyf6Yby wFAOK1HeiZZLXv5Nvxg== X-Proofpoint-GUID: mgAF2cBfD10G7M8BoMjpyWLSpaSvVf30 X-Authority-Analysis: v=2.4 cv=Jtf8bc4C c=1 sm=1 tr=0 ts=69b01e49 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=XyimcDP3rFlkA3yigAYA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: mgAF2cBfD10G7M8BoMjpyWLSpaSvVf30 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100118 On 3/6/26 10:02 AM, Krzysztof Kozlowski wrote: > On 24/02/2026 14:06, Konrad Dybcio wrote: >> On 2/24/26 1:13 PM, Abel Vesa wrote: >>> Introduce the initial support for the Qualcomm Eliza SoC. >>> It is a high-tier SoC designed for mobile platforms. >>> >>> The initial submission enables support for: >>> - CPU nodes with cpufreq and cpuidle support >>> - Global Clock Controller (GCC) >>> - Resource State Coordinator (RSC) with clock controller & genpd provider >>> - Interrupt controller >>> - Power Domain Controller (PDC) >>> - Vendor specific SMMU >>> - SPMI bus arbiter >>> - Top Control and Status Register (TCSR) >>> - Top Level Mode Multiplexer (TLMM) >>> - Debug UART >>> - Reserved memory nodes >>> - Interconnect providers >>> - System timer >>> - UFS >>> >>> Co-developed-by: Krzysztof Kozlowski >>> Signed-off-by: Krzysztof Kozlowski >>> Signed-off-by: Abel Vesa >>> --- >> >> [...] >> >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >> >> The values of the MPIDR register (also present in 'reg' of CPU nodes) >> suggest all these CPUs form a single logical cluster > > For reference: > > Data presented by firmware lies and different, e.g. fixed, firmware will > give you different results. All resources I found (several of them - > multiple docs, Block diagram from datasheet) say these are separate > clusters, so this is the topology we should be using currently. FWIW we discussed *MIDR*_EL1 (i.e. ""CPU ID"") with regards to the firmware lying. M*P*IDR represents the position of the core within the topology, and many, many recent Arm platforms have been reporting a single big cluster because of: https://developer.arm.com/documentation/100453/0401/The-DynamIQ-Shared-Unit/About-the-DSU We tended to agree with that and you'll notice almost all recent platforms have all the cores in a single cluster. I don't know if it was the right decision, I believe all these years no one cared to check/benchmark the impact that makes (if any) Konrad