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AJvYcCXz3BwnSBYEUk/A7Yb6rxZig63kvMLqf2v4un1xiIrGjr8QgyTytiMRbzTTx0AqP2TQq7y3VgInJK3Z6lM=@vger.kernel.org X-Gm-Message-State: AOJu0Yythw95jbzxvqTBQZRbOALAU2lLgJgHI8hgBHF78bDgCtbe1vxy 9S/gL/J4dgkCc3gYGJDrJe2A6d7a3TZX9X4VgHABr6akuf6NSna7vNQJEUNZozk= X-Google-Smtp-Source: AGHT+IERSShg0WJsWKe7p9IoZRZe8AE4cyMg7YOpn5Xi631+NWO8ocYGn/AacXCvFpRMXL3ss43sAg== X-Received: by 2002:a05:600c:3b16:b0:42f:80f4:ab31 with SMTP id 5b1f17b1804b1-4316163b593mr61999915e9.18.1729496828160; Mon, 21 Oct 2024 00:47:08 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a37b5asm3597813f8f.10.2024.10.21.00.47.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Oct 2024 00:47:07 -0700 (PDT) Message-ID: Date: Mon, 21 Oct 2024 10:47:03 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 03/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Content-Language: en-US To: Krzysztof Kozlowski Cc: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> <20241019084738.3370489-4-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 21.10.2024 10:32, Krzysztof Kozlowski wrote: > On Sat, Oct 19, 2024 at 11:47:29AM +0300, Claudiu wrote: >> From: Claudiu Beznea >> >> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, >> the tamper detector and a small general usage memory of 128B. >> >> The VBATTB controller controls the clock for the RTC on the Renesas >> RZ/G3S. The HW block diagram for the clock logic is as follows: >> >> +----------+ XC `\ >> RTXIN --->| |----->| \ +----+ VBATTCLK >> | 32K clock| | |----->|gate|-----------> >> | osc | XBYP | | +----+ > > Messed indent. Switch to spaces. > >> RTXOUT --->| |----->| / >> +----------+ ,/ >> >> One could connect as input to this HW block either a crystal or >> an external clock device. >> >> After discussions w/ Stephen Boyd the clock tree associated with this >> hardware block was exported in Linux as: >> >> input-xtal >> xbyp >> xc >> mux >> vbattclk >> >> where: >> - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) >> - xc, xbyp are mux inputs >> - mux is the internal mux >> - vbattclk is the gate clock that feeds in the end the RTC >> >> to allow selecting the input of the MUX though assigned-clock DT >> properties, using the already existing clock drivers and avoid adding >> other DT properties. >> >> This allows select the input of the mux based on the type of the >> connected input clock: >> - if the 32768 crystal is connected as input for the VBATTB, >> the input of the mux should be xc >> - if an external clock device is connected as input for the VBATTB the >> input of the mux should be xbyp > >> + clocks: >> + items: >> + - description: VBATTB module clock >> + - description: RTC input clock (crystal or external clock device) >> + >> + clock-names: >> + items: >> + - const: bclk >> + - const: rtx >> + >> + '#clock-cells': >> + const: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + items: >> + - description: VBATTB module reset >> + >> + quartz-load-femtofarads: >> + description: load capacitance of the on board crystal >> + enum: [ 4000, 7000, 9000, 12500 ] > > It's not required, so: > default: ? OK, I'll add the default. > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - power-domains >> + - resets >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + #include >> + #include >> + >> + clock-controller@1005c000 { >> + compatible = "renesas,r9a08g045-vbattb"; >> + reg = <0x1005c000 0x1000>; >> + interrupts = ; >> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; >> + clock-names = "bclk", "rtx"; >> + assigned-clocks = <&vbattb VBATTB_MUX>; >> + assigned-clock-parents = <&vbattb VBATTB_XC>; > > Why are you configuring internal clocks to internal parents? That's part > internal to this device, not DTS... or at least some explanation would > be useful. > > Best regards, > Krzysztof >