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X-CSE-ConnectionGUID: /eckuQY1Q0KhQBAE3GCIsQ== X-CSE-MsgGUID: ZH5JvV7SQSyOXxaLF+ZCsA== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15467897" X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="15467897" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2024 10:37:13 -0700 X-CSE-ConnectionGUID: bytPX4mWTAC4rbxWmHjyRQ== X-CSE-MsgGUID: YUSEM0WRQKaEAJCx+TZkZw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,247,1712646000"; d="scan'208";a="46757906" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.246.41.28]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jun 2024 10:37:08 -0700 Message-ID: Date: Tue, 18 Jun 2024 20:37:02 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf/x86/intel/pt: Update topa_entry base len to support 52-bit physical addresses To: Marco Cavenati , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, jolsa@kernel.org, irogers@google.com, kan.liang@linux.intel.com, tglx@linutronix.de, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com References: <20240618110617.22626-1-cavenati.marco@gmail.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20240618110617.22626-1-cavenati.marco@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/06/24 14:06, Marco Cavenati wrote: > Increase topa_entry base to 40 bits to accommodate page addresses in > systems with 52-bit physical addresses. > The Base Physical Address field (base) has a length of MAXPHYADDR - 12 as > stated in Intel's SDM chapter 33.2.7.2. > The maximum MAXPHYADDR is 52 as stated in SDM 4.1.4. > Therefore, the maximum base bit length is 40. > > Signed-off-by: Marco Cavenati Reviewed-by: Adrian Hunter Getting 'base' physical address wrong would presumably be bad, so: Fixes: 52ca9ced3f70 ("perf/x86/intel/pt: Add Intel PT PMU driver") Cc: stable@vger.kernel.org > --- > arch/x86/events/intel/pt.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/intel/pt.h b/arch/x86/events/intel/pt.h > index 96906a62aacd..f5e46c04c145 100644 > --- a/arch/x86/events/intel/pt.h > +++ b/arch/x86/events/intel/pt.h > @@ -33,8 +33,8 @@ struct topa_entry { > u64 rsvd2 : 1; > u64 size : 4; > u64 rsvd3 : 2; > - u64 base : 36; > - u64 rsvd4 : 16; > + u64 base : 40; > + u64 rsvd4 : 12; > }; > > /* TSC to Core Crystal Clock Ratio */