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Thu, 18 Jul 2024 01:21:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVCsM1BT5kQcMnEYC3j/H0GU4TuMnoheFVj1xqeFGH2ijUZ24HklGKePCFjzvCcGO+Wj2ItQ== X-Received: by 2002:a17:902:db06:b0:1fc:6028:b028 with SMTP id d9443c01a7336-1fc6028b1f4mr7517745ad.9.1721290907686; Thu, 18 Jul 2024 01:21:47 -0700 (PDT) Received: from [10.72.116.35] ([43.228.180.230]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc2712csm87732395ad.176.2024.07.18.01.21.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Jul 2024 01:21:47 -0700 (PDT) Message-ID: Date: Thu, 18 Jul 2024 16:21:42 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] KVM: arm64: Allow userspace to change ID_AA64PFR1_EL1 To: Oliver Upton Cc: Marc Zyngier , kvmarm@lists.linux.dev, Mark Brown , Eric Auger , Sebastian Ott , Cornelia Huck , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240718035017.434996-1-shahuang@redhat.com> <20240718035017.434996-3-shahuang@redhat.com> Content-Language: en-US From: Shaoqin Huang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Oliver, On 7/18/24 14:35, Oliver Upton wrote: > On Wed, Jul 17, 2024 at 11:50:15PM -0400, Shaoqin Huang wrote: >> Allow userspace to change the guest-visible value of the register with >> different way of handling: >> >> - Since the RAS and MPAM is not writable in the ID_AA64PFR0_EL1 >> register, RAS_frac and MPAM_frac are also not writable in the >> ID_AA64PFR1_EL1 register. >> >> - The MTE is controlled by an internal flag (KVM_ARCH_FLAG_MTE_ENABLED), >> so it's not writable. > > The flag isn't the relevant part, what's important about MTE is that it > already has a separate UAPI for controlling it (KVM_CAP_ARM_MTE). I'm not quite understand why KVM_ARCH_FLAG_MTE_ENABLED isn't the relevant part. I see this capability, when enable the KVM_CAP_ARM_MTE, it set the KVM_ARCH_FLAG_MTE_ENABLED in the kvm->arch.flags. And do you mean we should update it like "The MTE is controlled by a UAPI (KVM_CAP_ARM_MTE)"? > >> - For those fields which KVM doesn't know how to handle, they have >> are not exposed to the guest (being disabled in the register read >> accessor), those fields value will always be 0. Allow those fields >> writable is fine, since the userspace can only write 0 into those >> fields. Maybe in the future KVM know how to handle some of the >> fields, then they can be written into other value. >> So let them writable. >> Those fields include SME, RNDR_trap, NMI, GCS, THE, DF2, PFAR, >> MTE_frac, MTEX. > > This doesn't seem right. We're committing to a UAPI behavior the moment > these fields are advertised to userspace, which is rather difficult to > do for features that we don't even implement. > > Please only advertise the fields known to KVM and leave the others > unadvertised. Thanks a lot for pointing this out. Now I get the point, for those not implemented feature, they should not writable, so they're not advertised to userspace. > >> - The BT, SSBS, CSV2_frac don't introduce any new registers which KVM >> doesn't know how to handle, they can be written without ill effect. >> So let them writable. > > I think the handling of ARM_SMCCC_ARCH_WORKAROUND_2 needs to be updated > to consider the presence of FEAT_SSBS in the guest's ID registers. > Otherwise we'll wind up returning NOT_SUPPORTED and the guest will > conclude it is in a vulnerable state. I see that line of code, in the case ARM_SMCCC_ARCH_WORKAROUND_2: if (cpus_have_final_cap(ARM64_SSBS)) break; I guess we should update it with something like if (SYS_FIELD_GET(ID_AA64PFR1_EL1, SSBS, IDREG(kvm, SYS_ID_AA64PFR1_EL1)) != 0) Oliver, Is there any proper function or macro implement the checking like above? I don't find the similar checking in the code. Thanks, Shaoqin > -- Shaoqin