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During execution of FSGSBASE-related > instructions, the hardware actually checks whether this MSR > register's bit is set to determine whether to generate a #UD > exception. > When the CPU enters SMM mode and then returns via RSM, the CR4 > register is restored but the value of CR4.FSGSBASE is not > re-propagated to the MSR register. > As a result, after enabling CR4.FSGSBASE, once the CPU goes > through SMM mode, executing FSGSBASE-related instructions will > trigger a #UD exception.  /sigh, SMM strikes again. As this is a ucode bug, can it not be fixed with a ucode update to RSM? ~Andrew