From: Georgi Djakov <djakov@kernel.org>
To: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Odelu Kukatla <quic_okukatla@quicinc.com>,
Mike Tipton <quic_mdtipton@quicinc.com>,
Jagadeesh Kona <quic_jkona@quicinc.com>
Cc: Jeff Johnson <jeff.johnson@oss.qualcomm.com>,
Sibi Sankar <quic_sibis@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support
Date: Mon, 14 Apr 2025 12:58:00 +0300 [thread overview]
Message-ID: <c923c877-3d34-47c1-96ae-5ba6c3a39ebd@kernel.org> (raw)
In-Reply-To: <20250324183203.30127-4-quic_rlaggysh@quicinc.com>
On 24.03.25 20:31, Raviteja Laggyshetty wrote:
> EPSS on SA8775P has two instances, necessitating the creation of two
> device nodes with different compatibles due to the unique ICC node ID
> and name limitations in the interconnect framework. Add multidevice
> support for the OSM-L3 provider to dynamically obtain unique node IDs
> and register with the framework.
> EPSS topology includes a single master-slave pair within the same
> provider, the node linking logic is simplified by directly connecting
> the master node to the slave node.
>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> ---
> drivers/interconnect/qcom/osm-l3.c | 36 ++++++++++--------------------
> 1 file changed, 12 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
> index 6a656ed44d49..43e67d2116b9 100644
> --- a/drivers/interconnect/qcom/osm-l3.c
> +++ b/drivers/interconnect/qcom/osm-l3.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/args.h>
> @@ -48,16 +49,10 @@ struct qcom_osm_l3_icc_provider {
> /**
> * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
> * @name: the node name used in debugfs
> - * @links: an array of nodes where we can go next while traversing
> - * @id: a unique node identifier
> - * @num_links: the total number of @links
> * @buswidth: width of the interconnect between a node and the bus
> */
> struct qcom_osm_l3_node {
> const char *name;
> - u16 links[OSM_L3_MAX_LINKS];
Please remove also the #define for OSM_L3_MAX_LINKS, as it's unused now.
> - u16 id;
> - u16 num_links;
> u16 buswidth;
> };
>
BR,
Georgi
next prev parent reply other threads:[~2025-04-14 9:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-24 18:31 [PATCH V10 0/7]Add EPSS L3 provider support on SA8775P SoC Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 1/7] dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P Raviteja Laggyshetty
2025-03-24 18:31 ` [PATCH V10 2/7] interconnect: core: Add dynamic id allocation support Raviteja Laggyshetty
2025-04-14 9:57 ` Georgi Djakov
2025-03-24 18:31 ` [PATCH V10 3/7] interconnect: qcom: Add multidev EPSS L3 support Raviteja Laggyshetty
2025-04-14 9:58 ` Georgi Djakov [this message]
2025-03-24 18:32 ` [PATCH V10 4/7] interconnect: qcom: icc-rpmh: Add dynamic icc node id support Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 5/7] interconnect: qcom: sa8775p: " Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 6/7] arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider Raviteja Laggyshetty
2025-03-26 17:41 ` Dmitry Baryshkov
2025-03-24 18:32 ` [PATCH V10 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Raviteja Laggyshetty
2025-03-26 17:42 ` Dmitry Baryshkov
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