From: Rik van Riel <riel@surriel.com>
To: Jann Horn <jannh@google.com>, Borislav Petkov <bp@alien8.de>,
Ingo Molnar <mingo@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/mm: Limit INVLPGB to VA in invlpgb_flush_addr_nosync()
Date: Tue, 27 May 2025 19:39:56 -0400 [thread overview]
Message-ID: <c92a1f85eae86b49916ee1d0a8b3214962b18c4f.camel@surriel.com> (raw)
In-Reply-To: <20250527-x86-overbroad-invlpgb-v1-1-64ca98aa2a3a@google.com>
On Tue, 2025-05-27 at 23:56 +0200, Jann Horn wrote:
> The intent of invlpgb_flush_addr_nosync() is to flush a specific
> virtual
> address range, but INVLPGB_FLAG_VA is not set.
> If I understand AMD's documentation correctly, this means this will
> flush
> the entire TLB (except entries for guest ASIDs).
> That's safe, but seems like an unintentionally broad flush.
> Fix it by setting INVLPGB_FLAG_VA.
>
> Fixes: b7aa05cbdc52 ("x86/mm: Add INVLPGB support code")
> Signed-off-by: Jann Horn <jannh@google.com>
Reviewed-by: Rik van Riel <riel@surriel.com>
> ---
> I am not entirely sure about this; Rik, can you confirm if this was
> an
> oversight, or if there's actually a reason for not passing
> INVLPGB_FLAG_VA here?
This was totally an oversight, and probably lost
in one of many rounds of cleanups.
Good catch!
--
All Rights Reversed.
prev parent reply other threads:[~2025-05-27 23:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-27 21:56 Jann Horn
2025-05-27 23:39 ` Rik van Riel [this message]
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