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([2600:8803:e7e4:500:c69c:7b5c:ce9b:24be]) by smtp.gmail.com with ESMTPSA id 5614622812f47-45a5e1b1285sm3623783b6e.8.2026.01.08.07.56.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Jan 2026 07:56:58 -0800 (PST) Message-ID: Date: Thu, 8 Jan 2026 09:56:57 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/9] spi: Documentation: add page on multi-lane support To: Marcelo Schmitt Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org References: <20251219-spi-add-multi-bus-support-v4-0-145dc5204cd8@baylibre.com> <20251219-spi-add-multi-bus-support-v4-5-145dc5204cd8@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/8/26 6:44 AM, Marcelo Schmitt wrote: > Actually, one more thing ... > > On 12/19, David Lechner wrote: >> Add a new page to Documentation/spi/ describing how multi-lane SPI >> support works. This is uncommon functionality so it deserves its own >> documentation page. >> >> Signed-off-by: David Lechner >> --- > ... >> +- :c:macro:`SPI_MULTI_BUS_MODE_STRIPE`: Send or receive two different data words >> + at the same time, one on each lane. This means that the buffer needs to be >> + sized to hold data for all lanes. Data is interleaved in the buffer, with >> + the first word corresponding to lane 0, the second to lane 1, and so on. >> + Once the last lane is used, the next word in the buffer corresponds to lane >> + 0 again. Accordingly, the buffer size must be a multiple of the number of >> + lanes. This mode works for both reads and writes. >> + >> + Example:: >> + >> + struct spi_transfer xfer = { >> + .rx_buf = rx_buf, >> + .len = 2, >> + .multi_lane_mode = SPI_MULTI_BUS_MODE_STRIPE, >> + }; >> + >> + spi_sync_transfer(spi, &xfer, 1); >> + >> + Each tx wire has a different data word sent simultaneously:: > In this example, the controller is reading data so the rx wires have different > data word received? Yes, I tried to make that clear below by having a different value for each. > >> + >> + controller < data bits < peripheral >> + ---------- ---------------- ---------- >> + SDI 0 0-0-0-1-0-0-0-1 SDO 0 >> + SDI 1 1-0-0-0-1-0-0-0 SDO 1 >> + >> + After the transfer, ``rx_buf[0] == 0x11`` (word from SDO 0) and >> + ``rx_buf[1] == 0x88`` (word from SDO 1).