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([2a0d:3344:2712:7e10:4d59:d956:544f:d65c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8e26c8bsm14898388f8f.88.2025.07.15.05.52.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 05:52:30 -0700 (PDT) Message-ID: Date: Tue, 15 Jul 2025 14:52:29 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 1/5] dpll: zl3073x: Add support to get/set esync on pins To: Ivan Vecera , netdev@vger.kernel.org Cc: Prathosh Satish , Arkadiusz Kubalewski , Jiri Pirko , "David S. Miller" , Jakub Kicinski , linux-kernel@vger.kernel.org, Michal Schmidt , Petr Oros References: <20250710153848.928531-1-ivecera@redhat.com> <20250710153848.928531-2-ivecera@redhat.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <20250710153848.928531-2-ivecera@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/10/25 5:38 PM, Ivan Vecera wrote: > +static int > +zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, > + void *pin_priv, > + const struct dpll_device *dpll, > + void *dpll_priv, u64 freq, > + struct netlink_ext_ack *extack) > +{ > + struct zl3073x_dpll *zldpll = dpll_priv; > + struct zl3073x_dev *zldev = zldpll->dev; > + struct zl3073x_dpll_pin *pin = pin_priv; > + u32 esync_period, esync_width, output_div; > + u8 clock_type, out, output_mode, synth; > + u32 synth_freq; > + int rc; Minor nit: please respect the reverse christmas tree order above. > + > + out = zl3073x_output_pin_out_get(pin->id); > + > + /* If N-division is enabled, esync is not supported. The register used > + * for N-division is also used for the esync divider so both cannot > + * be used. > + */ > + switch (zl3073x_out_signal_format_get(zldev, out)) { > + case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: > + case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: > + return -EOPNOTSUPP; > + default: > + break; > + } > + > + guard(mutex)(&zldev->multiop_lock); > + > + /* Read output configuration into mailbox */ > + rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, > + ZL_REG_OUTPUT_MB_MASK, BIT(out)); > + if (rc) > + return rc; > + > + /* Read output mode */ > + rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); > + if (rc) > + return rc; > + > + /* Select clock type */ > + if (freq) > + clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; > + else > + clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; > + > + /* Update clock type in output mode */ > + output_mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; > + output_mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); > + rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, output_mode); > + if (rc) > + return rc; > + > + /* If esync is being disabled just write mailbox and finish */ > + if (!freq) > + goto write_mailbox; > + > + /* Get synth attached to output pin */ > + synth = zl3073x_out_synth_get(zldev, out); > + > + /* Get synth frequency */ > + synth_freq = zl3073x_synth_freq_get(zldev, synth); > + > + rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); > + if (rc) > + return rc; > + > + /* Compute and update esync period */ > + esync_period = synth_freq / (u32)freq / output_div; Here there is no check for output_div != 0, while such check is present into zl3073x_dpll_output_pin_esync_get(). Either is needed here, too, or should be dropped from the 'getter'. /P