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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b054dee693sm60611935ad.40.2026.03.16.23.10.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 23:10:26 -0700 (PDT) Message-ID: Date: Tue, 17 Mar 2026 14:10:20 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] phy: qcom: edp: Add eDP/DP mode switch support To: Vinod Koul , Neil Armstrong , Stephen Boyd , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20260302-edp_phy-v3-0-ca8888d793b0@oss.qualcomm.com> <20260302-edp_phy-v3-1-ca8888d793b0@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: <20260302-edp_phy-v3-1-ca8888d793b0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 7umVDXRdr5hljauBUFbUfWzJWGt2tcYE X-Authority-Analysis: v=2.4 cv=CKInnBrD c=1 sm=1 tr=0 ts=69b8f054 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=lzaHtpuxqINclaYr2a0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: 7umVDXRdr5hljauBUFbUfWzJWGt2tcYE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDA1MiBTYWx0ZWRfX4RxyRL6z3+VH z9AtI4GVn7jBp5apC6QR/rRb/jZatzqRNc1AUBpXu4PUODGPykJXBCAMg1/RL47PC/HqVObzUnP Sm0iEA1m9gDHmQcHv+KvIKJw3kxs9gasghAYLMVWSrZ8hoAEZT4ydD7HJFbEi3CZ2uzj6NEiI1w mOmK3XkTs7BSLQGDqWre5bz0c2H43jRQqola/fpwHzruKaHr4rrbhOBwd7IpMMIIb9r6Nj3uTip lJsd1a3yiFD9Sit2g8rZZlXzMM/2H0c+Lh3vPtBvfdw3XmmI7xKpPjJE2S+YxDBwyCv2AQimgby SHJHcQZ6oZQ4AboZSgRIEiOeVUxXLdg2Of2cyCosooZCCCBSvsGt0RJJz0x1u99XdutD4RARbJr ZEJ8u6pTTKl8RtaZ5bB9nYmRDySO9FGMXQHTcxv8chBOlbNevSsNLoi1cuNjSy3mjDMDI6WNn1c 52sMHNV52cBDa/GNSCQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_01,2026-03-16_06,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170052 On 3/2/2026 4:28 PM, Yongxing Mou wrote: > The eDP PHY supports both eDP&DP modes, each requires a different table. > The current driver doesn't fully support every combo PHY mode and use > either the eDP or DP table when enable the platform. In addition, some > platforms mismatch between the mode and the table where DP mode uses > the eDP table or eDP mode use the DP table. > > Clean up and correct the tables for currently supported platforms based on > the HPG specification. > > Here lists the tables can be reused across current platforms. > DP modeļ¼š > -sa8775p/sc7280/sc8280xp/x1e80100 > -glymur > eDP mode(low vdiff): > -glymur/sa8775p/sc8280xp/x1e80100 > -sc7280 > > Cc: stable@vger.kernel.org > Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") > Signed-off-by: Yongxing Mou > --- > drivers/phy/qualcomm/phy-qcom-edp.c | 90 ++++++++++++++++++++++--------------- > 1 file changed, 53 insertions(+), 37 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c > index 7372de05a0b8..36998326bae6 100644 > --- a/drivers/phy/qualcomm/phy-qcom-edp.c > +++ b/drivers/phy/qualcomm/phy-qcom-edp.c > @@ -87,7 +87,8 @@ struct qcom_edp_phy_cfg { > bool is_edp; > const u8 *aux_cfg; > const u8 *vco_div_cfg; > - const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; > + const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg; > + const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg; > const struct phy_ver_ops *ver_ops; > }; > > @@ -116,17 +117,17 @@ struct qcom_edp { > }; > > static const u8 dp_swing_hbr_rbr[4][4] = { > - { 0x08, 0x0f, 0x16, 0x1f }, > + { 0x07, 0x0f, 0x16, 0x1f }, > { 0x11, 0x1e, 0x1f, 0xff }, > { 0x16, 0x1f, 0xff, 0xff }, > { 0x1f, 0xff, 0xff, 0xff } > }; > > static const u8 dp_pre_emp_hbr_rbr[4][4] = { > - { 0x00, 0x0d, 0x14, 0x1a }, > + { 0x00, 0x0e, 0x15, 0x1a }, > { 0x00, 0x0e, 0x15, 0xff }, > { 0x00, 0x0e, 0xff, 0xff }, > - { 0x03, 0xff, 0xff, 0xff } > + { 0x04, 0xff, 0xff, 0xff } > }; > > static const u8 dp_swing_hbr2_hbr3[4][4] = { > @@ -150,6 +151,20 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = { > .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3, > }; > > +static const u8 dp_pre_emp_hbr_rbr_v8[4][4] = { > + { 0x00, 0x0e, 0x15, 0x1a }, > + { 0x00, 0x0e, 0x15, 0xff }, > + { 0x00, 0x0e, 0xff, 0xff }, > + { 0x00, 0xff, 0xff, 0xff } > +}; > + > +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_v8 = { > + .swing_hbr_rbr = &dp_swing_hbr_rbr, > + .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, > + .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr_v8, > + .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3, > +}; > + > static const u8 edp_swing_hbr_rbr[4][4] = { > { 0x07, 0x0f, 0x16, 0x1f }, > { 0x0d, 0x16, 0x1e, 0xff }, > @@ -158,7 +173,7 @@ static const u8 edp_swing_hbr_rbr[4][4] = { > }; > > static const u8 edp_pre_emp_hbr_rbr[4][4] = { > - { 0x05, 0x12, 0x17, 0x1d }, > + { 0x05, 0x11, 0x17, 0x1d }, > { 0x05, 0x11, 0x18, 0xff }, > { 0x06, 0x11, 0xff, 0xff }, > { 0x00, 0xff, 0xff, 0xff } > @@ -172,10 +187,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] = { > }; > > static const u8 edp_pre_emp_hbr2_hbr3[4][4] = { > - { 0x08, 0x11, 0x17, 0x1b }, > - { 0x00, 0x0c, 0x13, 0xff }, > - { 0x05, 0x10, 0xff, 0xff }, > - { 0x00, 0xff, 0xff, 0xff } > + { 0x0c, 0x15, 0x19, 0x1e }, > + { 0x0b, 0x15, 0x19, 0xff }, > + { 0x0e, 0x14, 0xff, 0xff }, > + { 0x0d, 0xff, 0xff, 0xff } > }; > > static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = { > @@ -193,25 +208,25 @@ static const u8 edp_phy_vco_div_cfg_v4[4] = { > 0x01, 0x01, 0x02, 0x00, > }; > > -static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = { > - { 0x05, 0x11, 0x17, 0x1d }, > - { 0x05, 0x11, 0x18, 0xff }, > - { 0x06, 0x11, 0xff, 0xff }, > - { 0x00, 0xff, 0xff, 0xff } > +static const u8 edp_swing_hbr2_hbr3_v3[4][4] = { > + { 0x06, 0x11, 0x16, 0x1b }, > + { 0x0b, 0x19, 0x1f, 0xff }, > + { 0x18, 0x1f, 0xff, 0xff }, > + { 0x1f, 0xff, 0xff, 0xff } > }; > > -static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] = { > +static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] = { > { 0x0c, 0x15, 0x19, 0x1e }, > - { 0x0b, 0x15, 0x19, 0xff }, > - { 0x0e, 0x14, 0xff, 0xff }, > + { 0x09, 0x14, 0x19, 0xff }, > + { 0x0f, 0x14, 0xff, 0xff }, > { 0x0d, 0xff, 0xff, 0xff } > }; > > -static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v5 = { > +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v3 = { > .swing_hbr_rbr = &edp_swing_hbr_rbr, > - .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, > - .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v5, > - .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5, > + .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3_v3, > + .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, > + .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v3, > }; > > static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = { > @@ -262,12 +277,7 @@ static int qcom_edp_phy_init(struct phy *phy) > DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, > edp->edp + DP_PHY_PD_CTL); > > - /* > - * TODO: Re-work the conditions around setting the cfg8 value > - * when more information becomes available about why this is > - * even needed. > - */ > - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) > + if (!edp->is_edp) > aux_cfg[8] = 0xb7; > > writel(0xfc, edp->edp + DP_PHY_MODE); > @@ -291,7 +301,7 @@ static int qcom_edp_phy_init(struct phy *phy) > > static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) > { > - const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg; > + const struct qcom_edp_swing_pre_emph_cfg *cfg; > unsigned int v_level = 0; > unsigned int p_level = 0; > u8 ldo_config; > @@ -299,11 +309,10 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur > u8 emph; > int i; > > - if (!cfg) > - return 0; > - > if (edp->is_edp) > - cfg = &edp_phy_swing_pre_emph_cfg; > + cfg = edp->cfg->edp_swing_pre_emph_cfg; > + else > + cfg = edp->cfg->dp_swing_pre_emph_cfg; > > for (i = 0; i < dp_opts->lanes; i++) { > v_level = max(v_level, dp_opts->voltage[i]); > @@ -564,20 +573,24 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = { > .is_edp = false, > .aux_cfg = edp_phy_aux_cfg_v5, > .vco_div_cfg = edp_phy_vco_div_cfg_v4, > - .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > .ver_ops = &qcom_edp_phy_ops_v4, > }; > > static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { > .aux_cfg = edp_phy_aux_cfg_v4, > .vco_div_cfg = edp_phy_vco_div_cfg_v4, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v3, > .ver_ops = &qcom_edp_phy_ops_v4, > }; > > static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = { > .aux_cfg = edp_phy_aux_cfg_v4, > .vco_div_cfg = edp_phy_vco_div_cfg_v4, > - .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > .ver_ops = &qcom_edp_phy_ops_v4, > }; > > @@ -585,7 +598,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { > .is_edp = true, > .aux_cfg = edp_phy_aux_cfg_v4, > .vco_div_cfg = edp_phy_vco_div_cfg_v4, > - .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > .ver_ops = &qcom_edp_phy_ops_v4, > }; > > @@ -766,7 +780,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = { > static struct qcom_edp_phy_cfg x1e80100_phy_cfg = { > .aux_cfg = edp_phy_aux_cfg_v4, > .vco_div_cfg = edp_phy_vco_div_cfg_v4, > - .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > .ver_ops = &qcom_edp_phy_ops_v6, > }; > > @@ -945,7 +960,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = { > static struct qcom_edp_phy_cfg glymur_phy_cfg = { > .aux_cfg = edp_phy_aux_cfg_v8, > .vco_div_cfg = edp_phy_vco_div_cfg_v8, > - .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5, > + .dp_swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg_v8, > + .edp_swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, > .ver_ops = &qcom_edp_phy_ops_v8, > }; > > Hi, maintanier, just a gentle ping on this patch in case it slipped through. Thanks!