From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4DF11DDC3C for ; Mon, 6 Jan 2025 14:31:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736173884; cv=none; b=bKhgeEjS91m7WgauBzLLjzpZfsTlNiN2qLKnvXV9u6aO3hk2TZ2Wec6TCjO3bVE6MR2nGQ9PH05g7Wz6fZZ+uy6L4VPbZvvPzp87xgr8Me/TA6SXsBoF5CekidwAR9Do7zfbE+c/g3I8VJY0waKfaZ6yTvPd2W0K2heSnhdVWZQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736173884; c=relaxed/simple; bh=JOPElY+rf0R9gMVqXy+A1D/5SwYkQkkRQQP+cfeF7Gs=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=DyfTh2kb0mrNG9bln4OmMmuFyuir4dF6Oq0QH4usMRkvlE//RHcKd4DM4gDpoPuAe18BPzSou0MKPMndFwSh6V9N0E/jWLe2vnNg3qDc7KR2Irc6NgPpypbmmH6xH6ThzBKS6bygqyuvtY/5Ag+nXv1tyodyEtrVD4IXugcLEBw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tUo3a-000000000J0-2aIE; Mon, 06 Jan 2025 09:26:14 -0500 Message-ID: Subject: Re: [PATCH 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes From: Rik van Riel To: Jann Horn Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Date: Mon, 06 Jan 2025 09:26:14 -0500 In-Reply-To: References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-10-riel@surriel.com> <96d1b007b3b88c43feac58d2646d675b94daf1fb.camel@surriel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Mon, 2025-01-06 at 14:04 +0100, Jann Horn wrote: > On Sat, Jan 4, 2025 at 3:55=E2=80=AFAM Rik van Riel wr= ote: >=20 > >=20 > > Then the only change needed to switch_mm_irqs_off > > would be to move the LOADED_MM_SWITCHING line to > > before choose_new_asid, to fully close the window. > >=20 > > Am I overlooking anything here? >=20 > I think that might require having a full memory barrier in > switch_mm_irqs_off to ensure that the write of LOADED_MM_SWITCHING > can't be reordered after reads in choose_new_asid(). Which wouldn't > be > very nice; we probably should avoid adding heavy barriers to the task > switch path... >=20 > Hmm, but I think luckily the cpumask_set_cpu() already implies a > relaxed RMW atomic, which I think on X86 is actually the same as a > sequentially consistent atomic, so as long as you put the > LOADED_MM_SWITCHING line before that, it might do the job? Maybe with > an smp_mb__after_atomic() and/or an explainer comment. > (smp_mb__after_atomic() is a no-op on x86, so maybe just a comment is > the right way. Documentation/memory-barriers.txt says > smp_mb__after_atomic() can be used together with atomic RMW bitop > functions.) >=20 That noop smp_mb__after_atomic() might be the way to go, since we do not actually use the mm_cpumask with INVLPGB, and we could conceivably skip updates to the bitmask for tasks using broadcast TLB flushing. > > >=20 > >=20 > > I'll add the READ_ONCE. > >=20 > > Will the race still exist if we wait on > > LOADED_MM_SWITCHING as proposed above? >=20 > I think so, since between reading the loaded_mm and reading the > loaded_mm_asid, the remote CPU might go through an entire task > switch. > Like: >=20 > 1. We read the loaded_mm, and see that the remote CPU is currently > running in our mm_struct. > 2. The remote CPU does a task switch to another process with a > different mm_struct. > 3. We read the loaded_mm_asid, and see an ASID that does not match > our > broadcast ASID (because the loaded ASID is not for our mm_struct). >=20 A false positive, where we do not clear the asid_transition field, and will check again in the future should be harmless, though. The worry is false negatives, where we fail to detect an out-of-sync CPU, yet still clear the asid_transition field. --=20 All Rights Reversed.