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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN1PEPF0000468C.mail.protection.outlook.com (10.167.243.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Mon, 8 Jun 2026 04:21:13 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Sun, 7 Jun 2026 23:21:13 -0500 Received: from [10.136.43.95] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Sun, 7 Jun 2026 23:21:10 -0500 Message-ID: Date: Mon, 8 Jun 2026 09:51:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/1] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems To: Marco Scardovi CC: , , , , , , , , References: <20260605103131.88711-1-scardracs@disroot.org> <20260606065756.4442-1-scardracs@disroot.org> <20260606065756.4442-2-scardracs@disroot.org> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <20260606065756.4442-2-scardracs@disroot.org> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: opWlY7u6GIT1N5zQ4W6woyKMVxmyz45mTKeDO/zXlR0+OyQt9GKbjFZtDgnDg/+fsbNPI+i/RA2W5AYO+60ssItNRLTncKcgaEohbKkVvduJE6aefEb1Wz9E5Uo9t5WCQEI2p09O/D1NwTN6l5beHYTTDyMWO/Wa6cnrKU/78Kgz+uN5o/3g3xgKQxUb/Cz3ix5H+egIByldMToVBjEykLcXeSPPH+vC0taxBUBs/ufGSewDSs85ft/NjoXTKDceJF08u+478g4o1vi4i9WpQb/waT0FryHWfHwVrGkpGZXW1TlVbJAWTi6xXEIOVkP+ogveCdbQTHd7YPOaawMvC+QFDIjdJnDK0u2TavNedLvJ5cYS8wm9SSYRSw+JqkLzxIHD6BpH5IFBObST5r8ytew94kWKfqagjjEvOc7N0k/TtNSNvKyctnF3RQWmfTKp X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2026 04:21:13.4889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28b6eab2-6980-4f24-a1e8-08dec5156063 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4351 Hello Marco, I don't mind the changes, except that it can be broken down into two patches as Mario suggested for easier backporting :-) Some notes below ... On 6/6/2026 12:27 PM, Marco Scardovi wrote: > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 8d55e2be825b..a35cf126e335 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -199,7 +199,7 @@ static inline int get_mode_idx_from_str(const char *str, size_t size) > > static DEFINE_MUTEX(amd_pstate_driver_lock); > > -static u8 msr_get_epp(struct amd_cpudata *cpudata) > +static int msr_get_epp(struct amd_cpudata *cpudata) > { > u64 value; > int ret; > @@ -215,12 +215,12 @@ static u8 msr_get_epp(struct amd_cpudata *cpudata) > > DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); > > -static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) > +static inline int amd_pstate_get_epp(struct amd_cpudata *cpudata) The change to return type and the amd_pstate_epp_cpu_init() bits should be Patch 1/2 with: Fixes: 555bbe67a622 ("cpufreq/amd-pstate: Convert all perf values to u8") and commit message stating the necessary error handling that is required if amd_pstate_get_epp() fails. > { > return static_call(amd_pstate_get_epp)(cpudata); > } > > -static u8 shmem_get_epp(struct amd_cpudata *cpudata) > +static int shmem_get_epp(struct amd_cpudata *cpudata) > { > u64 epp; > int ret; > @@ -525,10 +525,6 @@ static int shmem_init_perf(struct amd_cpudata *cpudata) > perf.lowest_perf = cppc_perf.lowest_perf; > WRITE_ONCE(cpudata->perf, perf); > WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); > - > - if (cppc_state == AMD_PSTATE_ACTIVE) > - return 0; > - And this should be Patch 2/2 with: Fixes: 2dd6d0ebf740 ("cpufreq: amd-pstate: Add guided autonomous mode") and a commit message that reads it is necessary for AMD_PSTATE_ACTIVE mode on shared memory system to toggle on AUTO_SEL_ENABLE based on the ACPI spec for CPPC v2 and below. > ret = cppc_get_auto_sel(cpudata->cpu, &auto_sel); > if (ret) { > pr_warn("failed to get auto_sel, ret: %d\n", ret); > @@ -1877,6 +1873,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) > struct amd_cpudata *cpudata; > union perf_cached perf; > struct device *dev; > + int default_epp; > int ret; > > /* > @@ -1926,6 +1923,14 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) > > policy->boost_supported = READ_ONCE(cpudata->boost_supported); > > + /* Cache the firmware programmed EPP */ > + default_epp = amd_pstate_get_epp(cpudata); > + if (default_epp < 0) { > + ret = default_epp; > + goto free_cpudata1; > + } > + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &cpudata->cppc_req_cached, default_epp); I would actually prefer this "cppc_req_cached" change to be a third patch that says caching the initial EPP saves on an unnecessary reprogramming later when the EPP is first set but I don't mind it being part of Patch 1 with a small note in the commit message. > + > /* > * Set the policy to provide a valid fallback value in case > * the default cpufreq governor is neither powersave nor performance. > @@ -1933,7 +1938,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) > if (amd_pstate_acpi_pm_profile_server() || > amd_pstate_acpi_pm_profile_undefined()) { > policy->policy = CPUFREQ_POLICY_PERFORMANCE; > - cpudata->epp_default_ac = cpudata->epp_default_dc = amd_pstate_get_epp(cpudata); > + cpudata->epp_default_ac = cpudata->epp_default_dc = default_epp; > cpudata->current_profile = PLATFORM_PROFILE_PERFORMANCE; > } else { > policy->policy = CPUFREQ_POLICY_POWERSAVE; -- Thanks and Regards, Prateek