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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bBm1QK6hmhPWmzpve/x3tYNyS91z/NYWK5OE1xvlcNiwIcNT6g6f8WFBMKTvq+bC3/3wIOecKGRFDyI+wQEq6Ie0wcNnFByRcAHTLH1CQlt2C5MA3l9H2OJt6stuAiof9x2LgDhkYzJBrMKns5Ds4YtXZve7Qi8rg89Rx1kz22KgUG+ZaQuESV6WN7m7IsoEraPujrvXnBsyXqUr+m3YcCNk7XObMR9ZBms9oqhsxnuOcqeLNUUOIieRjh0SEJV47b0PAFidxhck+WIcvBBXie8jLOL4VL6/tg56sOpjACNTGXAJkXvcEMuGUXp2IP9ZNbnvrsrpdaE9Gk4LwxfuR1hrrEmdruaQCScGcSQs/AF7VOEjTaJVEURoQAzECDC44QEBHeELn49vdMUZOYF21Z7n/IMhLI4+b6gR4a4oAjPvTJTeZEOhqcu5fZJRYcLc X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2026 05:08:44.4891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5dea64b6-024f-42f4-bd96-08de7362c8c8 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR10MB7449 On Mon, 2026-02-23 at 18:48 -0800, Jakub Kicinski wrote: > On Fri, 20 Feb 2026 09:41:57 +0530 Siddharth Vadapalli wrote: > > The 'irq_disabled' variable indicates the current state of the RX IRQ a= nd > > is used by the RX NAPI handler to determine whether the IRQ should be > > enabled. > >=20 > > Currently, 'irq_disabled' is set before actually disabling the IRQ by > > invoking disable_irq_nosync(). In an SMP environment, this leads to a r= ace > > condition wherein the processor taking the interrupt sets 'irq_disabled= ' > > while another processor executing a previous instance of the RX NAPI > > handler sees 'irq_disabled' set and invokes enable_irq() before the RX = IRQ > > is actually disabled by disable_irq_nosync(). This results in the follo= wing > > warning: > > Unbalanced enable for IRQ ... > >=20 > > Fix this by disabling the RX IRQ using disable_irq_nosync() before sett= ing > > 'irq_disabled'. >=20 > I'm not sure this is enough. The IRQ enable/disable serves as barriers > so the ordering is sane. I think the problem is that there are multiple > paths for Rx which may schedule NAPI, not just the path from the IRQ > handler. If the state changes have to be atomic you need a lock. I assume that state changes will be atomic since 'irq_disabled' is set in the HARD IRQ handler. Only the processor taking the interrupt will be able to update the state. Other processors can read the variable during their execution of the previous NAPI RX handlers. Only when 'irq_disabled' is set they will invoke 'enable_irq()'. So the race condition that you are referring to, is possible during the 'enable_irq()' path: In am65_cpsw_nuss_rx_poll() =3D> The RX NAPI Handler ... if (flow->irq_disabled) { flow->irq_disabled =3D false; ... enable_irq(); CPU1 sees irq_disabled being 'true' and before it updates it to 'false', if CPU2 also sees irq_disabled being 'true', both CPU1 and CPU2 will enter the IF-condition and eventually invoke enable_irq(). Please let me know if this is what you were referring to. I will use atomic APIs at all places to update 'irq_disabled'. Regards, Siddharth.