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Hermes SMTP Server) with ESMTPA ID e54a4390e0e3eda1a5bf77a8b1251c97; Sun, 08 Nov 2026 08:07:43 +0000 (UTC) Message-ID: Date: Sun, 8 Nov 2026 09:07:37 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH net-next v9 03/11] net: dsa: realtek: rtl8365mb: set speed for family D From: Mieczyslaw Nalewaj To: linusw@kernel.org, andrew@lunn.ch, olteanv@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, linux@armlinux.org.uk, luizluca@gmail.com, maxime.chevallier@bootlin.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, alvin.sipraga@analog.com, gusfmora@gmail.com, kuncy7@gmail.com, fabianotassotti@gmail.com, gabonpivovich@gmail.com, contact@c127.dev References: <9b73858d-fc09-4988-8bab-fd7b88db9412@yahoo.com> Content-Language: pl In-Reply-To: <9b73858d-fc09-4988-8bab-fd7b88db9412@yahoo.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.26943 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.yahoo On family C hardware, forcing a 2.5 Gbps link speed requires relying strictly on the HSGMII SerDes configuration block, while forcing a dummy 1 Gbps value inside the standard digital interface register. Family D introduces a dedicated hardware link speed value (5) for 2500M. The speed bitfield width has been expanded to 3 bits, splitting the most significant bit into a new separate register field (FORCE_SPEED2), which maps directly to a distinct per-port digital interface force layout. On family D the forced-mode configuration (link, duplex, pause, speed) is written to a per-port register at 0x12c0 + port instead of the per-extint register. The bit positions of TXPAUSE, RXPAUSE, LINK, DUPLEX and the low two speed bits are the same as on family C; the upper speed bits go to bits 13:12 (FORCE_SPEED2), so FORCE_EN (bit 12 on family C) is not set. A second per-port register at 0x12c8 + port enables the forced mode: the vendor RTL8367D API writes 0xFFFF there when the MAC is forced and 0 otherwise. This driver always forces the MAC, as on family C, so it writes 0xFFFF on every call, including link down. The family D branch is not reachable until the chip table entry is added in the last patch. Tested-by: Gustavo Foletto Mora Tested-by: Stanislaw Pal Signed-off-by: Mieczyslaw Nalewaj Reviewed-by: Linus Walleij --- drivers/net/dsa/realtek/rtl8365mb_main.c | 81 ++++++++++++++++++++---- 1 file changed, 68 insertions(+), 13 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c index b500c84..0d87d6b 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_main.c +++ b/drivers/net/dsa/realtek/rtl8365mb_main.c @@ -346,6 +346,8 @@ #define RTL8365MB_PORT_SPEED_10M 0 #define RTL8365MB_PORT_SPEED_100M 1 #define RTL8365MB_PORT_SPEED_1000M 2 +#define RTL8365MB_D_PORT_SPEED_2500M 5 +#define RTL8365MB_D_PORT_SPEED_MSB_MASK BIT(2) /* External interface force configuration registers 0~2 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ @@ -364,6 +366,26 @@ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK BIT(2) #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK GENMASK(1, 0) +/* bits[13:12]; bit 13 reserved, no defined speed value uses it yet */ +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK GENMASK(13, 12) + +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE 0x12c0 +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(_port) \ + (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE + (_port)) + +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE 0x12c8 +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(_port) \ + (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE + (_port)) + +/* Per-port force-mode enable. The vendor RTL8367D API + * (dal_rtl8367d_port_macForceLink_set()) treats it as an on/off switch for + * the whole forced configuration: all bits set when the MAC is forced, zero + * when it is not. The meaning of the individual bits is not documented. + * This driver always forces the MAC, as on family C, so all bits are set + * on every call, including link down. + */ +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK GENMASK(15, 0) + /* CPU port mask register - controls which ports are treated as CPU ports */ #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 #define RTL8365MB_CPU_PORT_MASK_MASK RTL8365MB_PORT_MASK @@ -1644,23 +1666,32 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, u32 r_duplex; u32 r_speed; u32 r_link; + bool is_d; int val; int ret; if (!extint) return -ENODEV; + is_d = rtl8365mb_is_d(priv); if (link) { /* Force the link up with the desired configuration */ r_link = 1; r_rx_pause = rx_pause ? 1 : 0; r_tx_pause = tx_pause ? 1 : 0; - /* The speed field has no value for 2.5 Gbps: the rate is - * determined by the HSGMII SerDes configuration, and the - * vendor driver programs the 1 Gbps value here. - */ - if (speed == SPEED_2500 || speed == SPEED_1000) { + if (speed == SPEED_2500) { + if (is_d) { + r_speed = RTL8365MB_D_PORT_SPEED_2500M; + } else { + /* The speed field has no value for 2.5 Gbps: + * the rate is determined by the HSGMII SerDes + * configuration, and the vendor driver programs + * the 1 Gbps value here. + */ + r_speed = RTL8365MB_PORT_SPEED_1000M; + } + } else if (speed == SPEED_1000) { r_speed = RTL8365MB_PORT_SPEED_1000M; } else if (speed == SPEED_100) { r_speed = RTL8365MB_PORT_SPEED_100M; @@ -1690,20 +1721,44 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex = 0; } - val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, + val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, r_tx_pause) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, r_rx_pause) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, r_duplex) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); - ret = regmap_write(priv->map, - RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), - val); - if (ret) - return ret; + FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, + r_speed & + RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK); + + if (is_d) { + /* Speed is 3 bits on family D: bits[1:0] go into FORCE_SPEED, + * bit[2] goes into FORCE_SPEED2 (register bit 12); only 2500M + * sets it. Register bit 13 is reserved. + */ + val |= FIELD_PREP(RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK, + FIELD_GET(RTL8365MB_D_PORT_SPEED_MSB_MASK, + r_speed)); + ret = regmap_write(priv->map, + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(port), + val); + if (ret) + return ret; + + ret = regmap_write(priv->map, + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(port), + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK); + if (ret) + return ret; + } else { + val |= FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1); + ret = regmap_write(priv->map, + RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), + val); + if (ret) + return ret; + } return 0; } -- 2.53.0