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Tue, 07 Jul 2026 00:57:07 -0700 (PDT) X-Received: by 2002:a05:622a:9c3:10b0:51b:f40b:2fa2 with SMTP id d75a77b69052e-51c4bd5a87bmr80135851cf.1.1783411027315; Tue, 07 Jul 2026 00:57:07 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15ad82311fsm75880366b.8.2026.07.07.00.57.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jul 2026 00:57:06 -0700 (PDT) Message-ID: Date: Tue, 7 Jul 2026 09:57:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] arm64: dts: qcom: Add GPU support for Kaanapali To: Akhil P Oommen Cc: Sean Paul , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Dmitry Baryshkov , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter References: <20260705-kaana-gpu-dt-v2-0-6ac53de56314@oss.qualcomm.com> <20260705-kaana-gpu-dt-v2-5-6ac53de56314@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=R7cz39RX c=1 sm=1 tr=0 ts=6a4cb154 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=w5vk1yBYWc5d-UbTd4AA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: nzjd-6_hB6fNpHACOe9I_Ya-FO2g-Rvn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDA3NSBTYWx0ZWRfX00r5l8Jl7YV2 yTdjK5nLpkcY+1tjvmB9K+tM1fRwIvNVVn0N7XiYBeWVLQ5X29jUawLQvaalZPxz5wlsyifrZ2E Mmvv6R4pTz0lLvtj+yLvWS7ulJWG8ObXm1O1ik3vWpHHA04iFTzMPPc8Ilepbq/efhYrwi3s391 1/Ye7PLmbrRed/I04O6FczNwPOGsrpbanQLOBaZWW4u50b9/chA+86z7Zes9zY+A+8an2SNQnRC 09uZTy+rANv7CP7vgFi2Evw57EGdYOP1K8+IjQ+csSXvcZwMkKMmW4zpnP05wTwktJXiyaTX9Bg tNVI2T9Oo9yk0px5natvb1xnGrgwGLU3+XCDz3Rp3hkGfXOY6wF+cU+NX0f8BaDa6qy5e24Zefm 7c5Gm0G3EqNkJOrkd5euseF0L7pstet9N/hCOq7oujfOoxDWK+jMJ9jd1qZntzT4oVPS7ub2hGk iPkZ7RrXleDX+GFq8Rg== X-Proofpoint-ORIG-GUID: nzjd-6_hB6fNpHACOe9I_Ya-FO2g-Rvn X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDA3NSBTYWx0ZWRfX4XNCS30vaO0U Ln57VZkHEqKZaMH3D3Am9i7DQ2/V4+s7fb7KiJ2YH+/EvzOxTSwZjuC8CQUGLgdJ2uNjOjPWkwy mOpdb6wtd8boDnSFgi4yX8S48Jc425s= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_01,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070075 On 7/6/26 10:06 PM, Akhil P Oommen wrote: > On 7/6/2026 3:07 PM, Konrad Dybcio wrote: >> On 7/5/26 10:00 AM, Akhil P Oommen wrote: >>> Adreno 840 present in Kaanapali SoC is the second generation GPU in >>> A8x family. It is based on the new slice architecture with 3 slices, >>> higher GMEM/caches etc. >>> >>> There is some re-arrangement in the reglist to properly cover maximum >>> register region. Other than this, the DT description is mostly similar >>> to the existing chipsets except the OPP tables. >>> >>> Reviewed-by: Dmitry Baryshkov >>> Signed-off-by: Akhil P Oommen >>> --- >> >> [...] >> >>> + qcom,gmu = <&gmu>; >>> + #cooling-cells = <2>; >>> + >>> + nvmem-cells = <&gpu_speed_bin>; >>> + nvmem-cell-names = "speed_bin"; >> >> This looks good to me, but I thought that on a8x, we're supposed to use >> the freq limiting register in CX_MISC - is either of them preferred? >> Or are they just hardwired to the same thing by chance > > I believe the other register would work, but I don't have a fused hw to > test. OTOH, this is what is commercialized. This is the answer then Konrad