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Fri, 26 Apr 2024 09:20:25 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43Q9KMaN025356 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 Apr 2024 09:20:22 GMT Received: from [10.218.10.146] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 26 Apr 2024 02:20:16 -0700 Message-ID: Date: Fri, 26 Apr 2024 14:50:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH V2 7/8] clk: qcom: Add GPUCC driver support for SM4450 To: Dmitry Baryshkov CC: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy , , , , , Taniya Das , "Jagadeesh Kona" , Imran Shaik , "Satya Priya Kakitapalli" References: <20240416182005.75422-1-quic_ajipan@quicinc.com> <20240416182005.75422-8-quic_ajipan@quicinc.com> Content-Language: en-US From: Ajit Pandey In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3uiw9dIqgbCoJcFFm8PKZL3HkWEE3PTx X-Proofpoint-ORIG-GUID: 3uiw9dIqgbCoJcFFm8PKZL3HkWEE3PTx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-26_09,2024-04-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 clxscore=1015 mlxscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404260060 On 4/17/2024 11:35 AM, Dmitry Baryshkov wrote: > On Tue, 16 Apr 2024 at 21:23, Ajit Pandey wrote: >> >> Add Graphics Clock Controller (GPUCC) support for SM4450 platform. >> >> Signed-off-by: Ajit Pandey >> --- >> drivers/clk/qcom/Kconfig | 9 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gpucc-sm4450.c | 805 ++++++++++++++++++++++++++++++++ >> 3 files changed, 815 insertions(+) >> create mode 100644 drivers/clk/qcom/gpucc-sm4450.c > > [skipped] > >> + >> +static int gpu_cc_sm4450_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + >> + regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); >> + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); >> + >> + /* Keep some clocks always enabled */ >> + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ > > My main concern here is the AON clocks. If we don't model > gpu_cc_demet_clk as a leaf clock, then gpu_cc_demet_div_clk_src > becomes a clock without children and can be disabled by Linux. > Likewise not modelling gpu_cc_cxo_aon_clk removes one of the voters on > gpu_cc_xo_clk_src, which can now be turned off by Linux. > Our usual recommendation is to model such clocks properly and to use > CLK_IS_CRITICAL or CLK_IGNORE_UNUSED to mark then as aon. > Thanks for review, actually if leaf (branch) clock is ON, hardware will take care of enabling and keeping the parent ON. So parent clocks won't get turned OFF in HW as long as branch clock is enabled. For clocks which are fixed rate (19.2MHz) and recommended to be kept ON forever from HW design, modelling and exposing clock structure in kernel will be a redundant code in kernel memory, hence as per earlier suggestion in previous thread such clocks are recommended to be kept enabled from probe. >> + >> + return qcom_cc_really_probe(pdev, &gpu_cc_sm4450_desc, regmap); >> +} >> + >> +static struct platform_driver gpu_cc_sm4450_driver = { >> + .probe = gpu_cc_sm4450_probe, >> + .driver = { >> + .name = "gpucc-sm4450", >> + .of_match_table = gpu_cc_sm4450_match_table, >> + }, >> +}; >> + >> +module_platform_driver(gpu_cc_sm4450_driver); >> + >> +MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver"); >> +MODULE_LICENSE("GPL"); >> -- >> 2.25.1 >> >> > > -- Thanks, and Regards Ajit