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Fri, 13 Mar 2026 00:08:11 -0700 (PDT) X-Received: by 2002:a05:6a00:21d4:b0:829:9cf1:642a with SMTP id d2e1a72fcca58-82a19911780mr1836652b3a.47.1773385690789; Fri, 13 Mar 2026 00:08:10 -0700 (PDT) Received: from [10.217.198.130] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a1e72cf33sm960207b3a.37.2026.03.13.00.08.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Mar 2026 00:08:10 -0700 (PDT) Message-ID: Date: Fri, 13 Mar 2026 12:38:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: Add Mahua SoC and CRD To: Dmitry Baryshkov , Gopikrishna Garmidi Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sibi.sankar@oss.qualcomm.com, pankaj.patil@oss.qualcomm.com, rajendra.nayak@oss.qualcomm.com, Raviteja Laggyshetty , Kamal Wadhwa References: <20260310054947.2114445-1-gopikrishna.garmidi@oss.qualcomm.com> <20260310054947.2114445-4-gopikrishna.garmidi@oss.qualcomm.com> Content-Language: en-US From: Manaf Meethalavalappu Pallikunhi In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA1NiBTYWx0ZWRfX61SDD2iF1Tab OTelWYvxFUa1hfexY3oDQGc+wY+H7wCfh9ISMfTxx4LYavgSuJhkZQoDameKxQcRgGcjCa4Xlif QrnSpR+WFXABmzElpMNb8/kjWCaB8TlqAb7piZ5Y91A0RZXR2mlBCLRn0A8K+rtOy6lyWlaRosx SQ4+O7Nrk8yLkJozMpk+ZmNl4wJxIunDehhYx/NDu/VJM4+uhu9aADUigkosl4FSxbH4scMYmCq V2m9ChC83HunUV6ngdT8McWZ1V8jdIbc5bwMJkyMWJ+Q+mkZ2v/OAgC4tNhNmfMka3XdI7p4DTq apyHd9YC0ZKKF6r5cfpYt2VEfN0BGN9MO6qUW5/NNXBorc+9dkCfh6AyIxlLR99SFzB9AMXE2O0 CPIW425YxC/+/gHzkHqzpNj3kSeGSkwD8jXs6JQeXThkE8j8d9O7EXj7wLUVPUpk94kbSbWEg/e zhrKBYHZCBlip/Ni7LQ== X-Proofpoint-ORIG-GUID: qIZRe_7dsZI3X_K6rDxqAEWI7bUeeshg X-Authority-Analysis: v=2.4 cv=C+7kCAP+ c=1 sm=1 tr=0 ts=69b3b7dc cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=q5pbYkwBJr7ivJQeOZAA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: qIZRe_7dsZI3X_K6rDxqAEWI7bUeeshg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130056 Hi Dmitry, On 3/12/2026 8:32 AM, Dmitry Baryshkov wrote: > On Mon, Mar 09, 2026 at 10:49:47PM -0700, Gopikrishna Garmidi wrote: >> Introduce support for the Mahua SoC and the CRD based on it. Some of >> the notable differences are the absent CPU cluster, interconnect, TLMM, >> thermal zones and adjusted PCIe west clocks. Everything else should >> work as-is. >> >> Co-developed-by: Raviteja Laggyshetty >> Signed-off-by: Raviteja Laggyshetty >> Co-developed-by: Kamal Wadhwa >> Signed-off-by: Kamal Wadhwa >> Co-developed-by: Manaf Meethalavalappu Pallikunhi >> Signed-off-by: Manaf Meethalavalappu Pallikunhi >> Signed-off-by: Gopikrishna Garmidi >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- >> arch/arm64/boot/dts/qcom/mahua-crd.dts | 21 + >> arch/arm64/boot/dts/qcom/mahua.dtsi | 1040 ++++++++++++++++++ >> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 2 +- >> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 4 +- >> 6 files changed, 1066 insertions(+), 4 deletions(-) >> create mode 100644 arch/arm64/boot/dts/qcom/mahua-crd.dts >> create mode 100644 arch/arm64/boot/dts/qcom/mahua.dtsi >> >> + >> +&tsens4 { >> + #qcom,sensors = <13>; > > This matches the value in glymur.dtsi my bad, it is supposed to be 11 for mahua. It is taken care in below thermal zone list. Will update in next revision. > >> +}; >> + >> +&tsens5 { >> + #qcom,sensors = <15>; > > This one is indeed different. > >> +}; >> + >> +/ { >> + thermal_zones: thermal-zones { > > You've completely rewritten thermal zones. Can we patch them instead? > The difference would be more obvious this way. Out of the 69 sensors in Mahua, around 27 sensors show discrepancies when compared with Glymur. These differences are not limited to sensor ID updates alone; due to changes in sensor mapping, some nodes trip and cooling binding require node-level updates. Additionally, approximately 23 thermal zone sensor nodes need to be deleted individually, since Glymur has a total of 92 sensors. Considering this, would it be better to delete the entire set of thermal zones and reconfigure them specifically for Mahua to improve clarity and maintainability? I noticed that Purwa followed a similar approach. Thanks, Manaf > >