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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33b513ae55dsm6546465a91.25.2025.10.09.03.43.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Oct 2025 03:43:39 -0700 (PDT) Message-ID: Date: Thu, 9 Oct 2025 16:13:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox To: Konrad Dybcio , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-6-24b601bbecc0@oss.qualcomm.com> Content-Language: en-US From: Sibi Sankar In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=ZJzaWH7b c=1 sm=1 tr=0 ts=68e791dd cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=JW5fmLY_j8n8a94A13AA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: PcfyADDxLoGJ4AAe9FhHM05V2TJi752E X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfXxOQX8NhTNfNz QgAujlMSSZiaI4hMQjLwBbQQa6rj1USvK0C2Jhmp+IEUHDXgF4WxlATco4T+ZGhb7V3aWk7AsRW kacvFcWC6vytpYAGMidIfORgB0GjK/iJwMYf41fCE6DjB0a67q8oM5xE0pLH0K6yhJmLqLH4LPR 7JiUdeBFU5gfgdSKAkoUgjAdX326xFIh/VPvaRMr6KE+WidLwoJW2lRELXzspXNehgPtMBY67Tm ElmBWwOUYYKkUrPuVbdJZjVQfNOdGlzQ+j9Exosanu8R3JXlK+fNoVTrV9fOiARRVdKt5G8AidA XwE7H2ZnM7Cem/F7HdZxrQ+GA4vBUoSe+BPt3bNu8m9Tfdk+Dj/+V3PDzFVxSaxQNtSeanzMJA6 3Q2NFKQLu/ewIKRBK3luGCfOzehhqw== X-Proofpoint-GUID: PcfyADDxLoGJ4AAe9FhHM05V2TJi752E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-09_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 On 9/25/2025 3:59 PM, Konrad Dybcio wrote: > On 9/25/25 8:32 AM, Pankaj Patil wrote: >> From: Sibi Sankar >> >> Enable pdp0 mailbox node on Glymur SoCs. >> >> Signed-off-by: Sibi Sankar >> Signed-off-by: Pankaj Patil >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >> index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644 >> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> @@ -4065,6 +4065,14 @@ watchdog@17600000 { >> interrupts = ; >> }; >> >> + pdp0_mbox: mailbox@17610000 { >> + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; >> + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; > 1 a line, please Hey Konrad, Thanks for taking time to review the series :) Will fix it in the next re-spin. >> + interrupts = ; > I see this has 3 channels, with 3 separate IRQs (but one pair of address > spaces) - should we extend this description? It has a single IRQ and each bit corresponds to a channel.  The mbox theoretically hold as many channel as the number of bits. The third channel here is used for logging and is disabled on devices out in the wild. > >> + #mbox-cells = <1>; >> + qcom,rx-chans = <0x7>; > This further seems to confirm what I found (BIT(0) | BIT(1) | BIT(2) == 0x7) > however this property doesn't exist upstream.. Ack, this seems to have picked up erroneously and isn't needed upstream and can be dropped safely. This was needed downstream because they share the same rx register space across multiple instances. This wouldn't be possible upstream and we would be exposing all mailboxes that uses the rx space in the same instance and extend mbox cells to 2 to support this in case when it is needed in the future. > Konrad