From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 042CBC433F5 for ; Thu, 5 May 2022 14:17:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379395AbiEEOVK (ORCPT ); Thu, 5 May 2022 10:21:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231845AbiEEOVH (ORCPT ); Thu, 5 May 2022 10:21:07 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CED1056410; Thu, 5 May 2022 07:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651760247; x=1683296247; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=rZ47qt24YNYTgsRKaNj73tbOKZqNZZlJgOgPoM3XEqg=; b=QiSGtH8V3kiNSKN4kd0suB0lgF3cmx758OuHGzYXiXKlhZSk6FqtRZEu piBMVViuQ8bIM/1ZaqTU1lPBkYyHpTNrrXsaKwCy5yJqXmTYOvmQaZNBc T5jSqFiA0P83SAZBnbXuXcUHMVq615LovjIGFRJD0ZXxR3To70SEBmhdt 8=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 May 2022 07:17:27 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 07:17:27 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 07:17:27 -0700 Received: from [10.216.34.221] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 07:17:22 -0700 Message-ID: Date: Thu, 5 May 2022 19:47:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v13 4/4] arm64: dts: qcom: sc7280-herobrine: Add lpi pinmux properties for CRD 3.0/3.1 Content-Language: en-US To: Matthias Kaehlcke CC: , , , , , , , , , , , Venkata Prasad Potturu References: <1651662987-11704-1-git-send-email-quic_srivasam@quicinc.com> <1651662987-11704-5-git-send-email-quic_srivasam@quicinc.com> From: Srinivasa Rao Mandadapu Organization: Qualcomm In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/5/2022 4:01 AM, Matthias Kaehlcke wrote: Thanks for Your time Matthias!!! > On Wed, May 04, 2022 at 04:46:27PM +0530, Srinivasa Rao Mandadapu wrote: >> Add LPASS LPI pinctrl properties, which are required for Audio >> functionality on herobrine based platforms of rev5+ >> (aka CRD 3.0/3.1) boards. >> >> Signed-off-by: Srinivasa Rao Mandadapu >> Co-developed-by: Venkata Prasad Potturu >> Signed-off-by: Venkata Prasad Potturu >> --- >> arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 63 +++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts >> index deaea3a..dc61bad 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts >> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts >> @@ -110,6 +110,69 @@ ap_ts_pen_1v8: &i2c13 { >> * - If a pin is totally internal to Qcard then it gets Qcard name. >> * - If a pin is not hooked up on Qcard, it gets no name. >> */ >> +&lpass_dmic01_clk { >> + drive-strength = <8>; >> + bias-disable; >> +}; >> + >> +&lpass_dmic01_data { >> + bias-pull-down; >> +}; >> + >> +&lpass_dmic01_clk_sleep { >> + drive-strength = <2>; >> +}; > should be after 'lpass_dmic01_clk' Okay. Will sort accordingly. > >> + >> +&lpass_dmic23_clk { >> + drive-strength = <8>; >> + bias-disable; >> +}; >> + >> +&lpass_dmic23_data { >> + bias-pull-down; >> +}; >> + >> +&lpass_dmic23_clk_sleep { >> + drive-strength = <2>; >> +}; > see above Okay. > >> + >> +&lpass_rx_swr_clk { >> + drive-strength = <2>; >> + slew-rate = <1>; >> + bias-disable; >> +}; >> + >> +&lpass_rx_swr_data { >> + drive-strength = <2>; >> + slew-rate = <1>; >> + bias-bus-hold; >> +}; >> + >> +&lpass_rx_swr_clk_sleep { >> + drive-strength = <2>; > drive strengh is the same as for 'lpass_rx_swr_clk', can be omitted? Okay. Will remove it. > >> + bias-pull-down; >> +}; > see 'lpass_dmic23_clk_sleep' Okay. Will sort accordingly. > >> + >> +&lpass_rx_swr_data_sleep { >> + drive-strength = <2>; > is drive strength really needed here? Okay. Will remove it. > >> + bias-pull-down; >> +}; >> + >> +&lpass_tx_swr_clk { >> + drive-strength = <2>; >> + slew-rate = <1>; >> + bias-disable; >> +}; >> + >> +&lpass_tx_swr_data { >> + slew-rate = <1>; >> + bias-bus-hold; >> +}; >> + >> +&lpass_tx_swr_clk_sleep { >> + drive-strength = <2>; > is drive strength really needed here? Okay. Will remove it. > >> + bias-pull-down; >> +}; > see 'lpass_dmic23_clk_sleep' Okay. Will sort accordingly. > >> >> &mi2s1_data0 { >> drive-strength = <6>; >> -- >> 2.7.4 >>