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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b983398d82dsm611474866b.62.2026.03.24.02.22.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 02:22:37 -0700 (PDT) Message-ID: Date: Tue, 24 Mar 2026 10:22:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src To: Dmitry Baryshkov Cc: Pengyu Luo , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260321095029.2259489-1-mitltlatltl@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=GIIF0+NK c=1 sm=1 tr=0 ts=69c257e0 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=qC_FGOx9AAAA:8 a=eV-8nqNh-aYkQHMPB9UA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=fsdK_YakeE02zTmptMdW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDA3NCBTYWx0ZWRfX9/e/BJvv/kpf tNUltWrz/802yd7HleAAensyetxyi/D5wDcLf8Xee8sn3ndm342W8NGUcxfnxE+smnOFl5IWlvW dLrTjmixx/pLEdXrTwXmrKy4kUb1BDcxo6Jcf8/cCEFXlsa/s5m8vCJiia3+P0vKIxE5U8XK1FV LsCHXTfpEkwm8Kp0yuedU3psP8xWNBfBqOzOkdECZBXUSJpsIWpGCTPvHC3uYGfER+T8BLmPlVz sK8wfO7lprl1clYTh/QdpDoDYifQA3QSdiKmOHtSNIeXjHAEbEGA5jiumXPSXHzoWFBp/4yDr/L uhjyS5z0UaeuWE3WnQYb3lpdM4YR0IHoxMRzbchB1HU7b2YnE8exEGa0TxVD9y5H/jLw5oEqJBP GzUMaCltl/4w8TacAheLH+aZPZy2baKb2r0SWWgWR+m0XmguYCAFq4zdFRcnljAi8nL4chIfyaY fYIxpRmLq5yHojKTakg== X-Proofpoint-GUID: KQ2S2N0gTekp3VQ-B1dYWY8N4jtyaoDC X-Proofpoint-ORIG-GUID: KQ2S2N0gTekp3VQ-B1dYWY8N4jtyaoDC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_02,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240074 On 3/23/26 8:23 PM, Dmitry Baryshkov wrote: > On Mon, Mar 23, 2026 at 01:54:29PM +0100, Konrad Dybcio wrote: >> On 3/21/26 10:50 AM, Pengyu Luo wrote: >>> Recently, when testing 10-bit dsi C-PHY panel, clks are different >>> from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk >>> now (dsiclk_sel = 0)) And we failed to set dsiclk's children. >>> >>> dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000 >>> >>> byteclk was set first to 108120000, so the vco rate was set to >>> 108120000 * 7 * 1 * 1 = 756840000. When we was trying to set >>> 172992000 on mdss_pixel_clk_src later. >>> >>> Since there was no matched ratio, we failed to set it. And dsiclk >>> divider ratio was set to 15:1 (wrong cached register value 0xf and >>> didn't update), we finally got 50455997, apparently wrong. >>> >>> dsi0vco_clk 1 1 0 756839941 >>> dsi0_pll_out_div_clk 1 1 0 756839941 >>> dsi0_pll_post_out_div_clk 0 0 0 216239983 >>> dsi0_pll_bit_clk 2 2 0 756839941 >>> dsi0_phy_pll_out_dsiclk 2 2 0 50455997 >>> disp_cc_mdss_pclk1_clk_src 1 1 0 50455997 >>> dsi0_pll_by_2_bit_clk 0 0 0 378419970 >>> dsi0_phy_pll_out_byteclk 2 2 0 108119991 >>> disp_cc_mdss_byte1_clk_src 2 2 0 108119991 >>> >>> Downstream clk_summary shows the mdss_pixel_clk_src support the >>> ratio(35:16) >>> >>> dsi0_phy_pll_out_dsiclk 2 2 0 378420000 >>> disp_cc_mdss_pclk1_clk_src 1 1 0 172992000 >>> dsi0_phy_pll_out_byteclk 2 2 0 108120000 >>> disp_cc_mdss_byte1_clk_src 2 2 0 108120000 >>> >>> After checking downstream source, 15:4 also seems to be supported, >>> add them two. >> >> I don't see that, not even in the newest releases.. Is there even a reason >> we have to list these divider pairs in the first place? > > https://git.codelinaro.org/clo/la/kernel/qcom/-/commit/f7aec4359448d25c8a8d21ad8e8733d61f6b69ab Ahh branching.. > We need those dividers to correctly program pclk RCG2 clocks. I would assume that's the case, but perhaps the real answer is "because we don't want to try all possible combinations" Konrad