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Wed, 11 Oct 2023 10:45:02 GMT Received: from [10.216.52.55] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 11 Oct 2023 03:44:53 -0700 Message-ID: Date: Wed, 11 Oct 2023 16:14:50 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v1 5/5] arm64: dts: qcom: sa8775p: Add ep pcie0 controller node Content-Language: en-US To: Manivannan Sadhasivam CC: , , , , , , , , , , , , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , Vinod Koul , , , , , , References: <1695218113-31198-1-git-send-email-quic_msarkar@quicinc.com> <1695218113-31198-6-git-send-email-quic_msarkar@quicinc.com> <20230921094823.GE2891@thinkpad> From: Mrinmay Sarkar In-Reply-To: <20230921094823.GE2891@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: txDmBbCPzhrIWJ1FGyxQQng_l1FT9Qe8 X-Proofpoint-GUID: txDmBbCPzhrIWJ1FGyxQQng_l1FT9Qe8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-11_08,2023-10-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310110094 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/21/2023 3:18 PM, Manivannan Sadhasivam wrote: > On Wed, Sep 20, 2023 at 07:25:12PM +0530, Mrinmay Sarkar wrote: >> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. >> > It would be good to add more info in the commit message, like PCIe Gen, lane > info, IP revision etc... > >> Signed-off-by: Mrinmay Sarkar >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 45 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 9f4f58e8..5571131 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -2600,4 +2600,49 @@ >> >> status = "disabled"; >> }; >> + >> + pcie0_ep: pcie-ep@1c00000 { >> + compatible = "qcom,sa8775p-pcie-ep"; >> + reg = <0x0 0x01c00000 0x0 0x3000>, >> + <0x0 0x40000000 0x0 0xf20>, >> + <0x0 0x40000f20 0x0 0xa8>, >> + <0x0 0x40001000 0x0 0x4000>, >> + <0x0 0x40200000 0x0 0x100000>, >> + <0x0 0x01c03000 0x0 0x1000>, >> + <0x0 0x40005000 0x0 0x2000>; >> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", >> + "mmio", "dma"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; >> + >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a"; >> + >> + interrupts = , >> + , >> + ; >> + >> + interrupt-names = "global", "doorbell", "dma"; >> + >> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; >> + interconnect-names = "pcie-mem", "cpu-pcie"; >> + > Don't you need iommu property? > >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "core"; >> + power-domains = <&gcc PCIE_0_GDSC>; >> + phys = <&pcie0_phy>; >> + phy-names = "pciephy"; >> + max-link-speed = <3>; > Gen 3? there is some stability issue with gen4 so going with gen3 as of now. Will update once issue is resolved. Thanks, Mrinmay >> + num-lanes = <2>; > Only 2 lanes? Or the other one has 4 lanes? > > - Mani pcie0 has lane2 and pcie1 has lane4 configuration. Thanks, Mrinmay >> + >> + status = "disabled"; >> + }; >> }; >> -- >> 2.7.4 >>