From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-181.mta1.migadu.com (out-181.mta1.migadu.com [95.215.58.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A01FF239085 for ; Mon, 12 Jan 2026 07:54:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.181 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768204495; cv=none; b=qvb8M73T6eM1L7YDbXyhrgwJ4PEP3ZUOf48zM7Qn6JsUR+0MM1bn5aVJU68YrMcgVGhd6ycABGdEQNDQFCBVGwH6DtlziLt2GxaCBEjY9/XQRI9OOvfrGNAKGc0pnq8UMkzDep8R9XIVUjdBnNVPCGDsiVSb59lrI9M5fuJu7I4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768204495; c=relaxed/simple; bh=oYLWwYNzKYVJ9Gy+BbCbOzruWPGCAyS2ltUclbM6h0A=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=fM00eAWafvIk+J38fICD8XECcztjaeXhBZGMHAgApHdwjuMufGpvO/Q8XplmXLFri0LIojOum8JbrxaD2SgPsb/1T1uEWW+OLH6iHqKhw1/Fh/n22qSWsKYkUqNkYwuxHKQG2F+3vPTfwmvpqpcyv0yocPd+CQSN59KOUphNYEA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=X8XpVIoW; arc=none smtp.client-ip=95.215.58.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="X8XpVIoW" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1768204481; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RWKyeRy2s78zQYIRD23rnsmDUGzSSXuD7HSb16jI09M=; b=X8XpVIoWRpf1zniVfJmlUz/iAe9mQOQI+sFVIJ3u4aFKghNOX5E01hs9WDdYqJw10TCzjP xi6uUiwRRUO1M/m+BDikRUeam1XjYRU4mDeX8gWZH5+8eJAnps9dyDQYzoHSgXQGqBTFB1 JyE+HaYi4uUCRSOBp+Mklm7Vug25GGf14OJGy0eN8K5Pe16MT0m6RToyXSgjBlv8raXW2E 8PViDFL9vsLpxg3W2bEKA9k1PeWIB+oS8iDf8Gq8VAWXUJP8iyQFjXlAxLklMSnTv83RFD JAu3Ok02UyofsPkrMyFQfCCmX2IWGapo/KCmzyiHhlV8sGrvd23p+tuENLYWCw== Date: Mon, 12 Jan 2026 04:54:28 -0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2] drm/msm/dpu: Filter modes based on adjusted mode clock To: Xilin Wu , Jessica Zhang , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio References: <20250506-filter-modes-v2-1-c20a0b7aa241@oss.qualcomm.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Val Packett In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT On 1/12/26 3:31 AM, Xilin Wu wrote: > On 5/7/2025 9:38 AM, Jessica Zhang wrote: >> Filter out modes that have a clock rate greater than the max core clock >> rate when adjusted for the perf clock factor >> >> This is especially important for chipsets such as QCS615 that have lower >> limits for the MDP max core clock. >> >> Since the core CRTC clock is at least the mode clock (adjusted for the >> perf clock factor) [1], the modes supported by the driver should be less >> than the max core clock rate. >> >> [1] >> https://elixir.bootlin.com/linux/v6.12.4/source/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c#L83 >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Jessica Zhang >> --- > > Hi. This patch effectively filters out the 3840x2160@120Hz mode on > SC8280XP CRD. The calculated adjusted_mode_clk is 623700, which > slightly exceeds the supported max core clock of 600000. > > However, 4K 120Hz works flawlessly with the limit removed on this > platform. I even tried connecting two 4K 120Hz displays, and they can > work properly simultaneously. Is it possible to bring back support for > this mode, or adjust the limits? hm, interestingly on X1E80100 we didn't hit *that* limit, the adjusted_mode_clk (576318) was only above what disp_cc_mdss_mdp_clk was set to (575000), and reducing the clk_inefficiency_factor from 105 to 104 was enough to lower it. https://gitlab.freedesktop.org/drm/msm/-/issues/38#note_3216051 I guess it's also sink dependent, like if the mode for some monitors has much more front/back porch etc.? What's the entire modeline that resulted in 623700? ~val