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From: Yang Shi <yang@os.amperecomputing.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: "Christoph Lameter (Ampere)" <cl@gentwo.org>,
	will@kernel.org, anshuman.khandual@arm.com, david@redhat.com,
	scott@os.amperecomputing.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [v5 PATCH] arm64: mm: force write fault for atomic RMW instructions
Date: Tue, 9 Jul 2024 15:29:58 -0700	[thread overview]
Message-ID: <cb0bd817-6948-4944-ab09-4ec2aba41cfa@os.amperecomputing.com> (raw)
In-Reply-To: <Zo2C4eXr5_9kifyO@arm.com>



On 7/9/24 11:35 AM, Catalin Marinas wrote:
> On Tue, Jul 09, 2024 at 10:56:55AM -0700, Yang Shi wrote:
>> On 7/4/24 3:03 AM, Catalin Marinas wrote:
>>> I haven't figured out what the +24% case is in there, it seems pretty
>>> large.
>> I think I ran the test much more iterations and I didn't see such outlier
>> anymore.
> That's good, thanks for confirming.
>
>>> What you haven't benchmarked (I think) is the case where the instruction
>>> is in an exec-only mapping. The subsequent instruction read will fault
>>> and it adds to the overhead. Currently exec-only mappings are not
>>> widespread but I heard some people planning to move in this direction as
>>> a default build configuration.
>> I tested exec-only on QEMU tcg, but I don't have a hardware supported EPAN.
>> I don't think performance benchmark on QEMU tcg makes sense since it is
>> quite slow, such small overhead is unlikely measurable on it.
> Yeah, benchmarking under qemu is pointless. I think you can remove some
> of the ARM64_HAS_EPAN checks (or replaced them with ARM64_HAS_PAN) just
> for testing. For security reason, we removed this behaviour in commit
> 24cecc377463 ("arm64: Revert support for execute-only user mappings")
> but it's good enough for testing. This should give you PROT_EXEC-only
> mappings on your hardware.

Thanks for the suggestion. IIUC, I still can emulate exec-only even 
though hardware doesn't support EPAN? So it means reading exec-only area 
in kernel still can trigger fault, right?

And 24cecc377463 ("arm64: Revert support for execute-only user 
mappings") can't be reverted cleanly by git revert, so I did it manually 
as below.

diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 6a8b71917e3b..0bdedd415e56 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -573,8 +573,8 @@ static int __kprobes do_page_fault(unsigned long 
far, unsigned long esr,
                 /* Write implies read */
                 vm_flags |= VM_WRITE;
                 /* If EPAN is absent then exec implies read */
-               if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN))
-                       vm_flags |= VM_EXEC;
+               //if (!alternative_has_cap_unlikely(ARM64_HAS_EPAN))
+               //      vm_flags |= VM_EXEC;
         }

         if (is_ttbr0_addr(addr) && is_el1_permission_fault(addr, esr, 
regs)) {
diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c
index 642bdf908b22..d30265d424e4 100644
--- a/arch/arm64/mm/mmap.c
+++ b/arch/arm64/mm/mmap.c
@@ -19,7 +19,7 @@ static pgprot_t protection_map[16] __ro_after_init = {
         [VM_WRITE]                                      = PAGE_READONLY,
         [VM_WRITE | VM_READ]                            = PAGE_READONLY,
         /* PAGE_EXECONLY if Enhanced PAN */
-       [VM_EXEC]                                       = 
PAGE_READONLY_EXEC,
+       [VM_EXEC]                                       = PAGE_EXECONLY,
         [VM_EXEC | VM_READ]                             = 
PAGE_READONLY_EXEC,
         [VM_EXEC | VM_WRITE]                            = 
PAGE_READONLY_EXEC,
         [VM_EXEC | VM_WRITE | VM_READ]                  = 
PAGE_READONLY_EXEC,


Is it correct? Just wanted to make sure I did the right thing before 
running test.

>


  reply	other threads:[~2024-07-09 22:30 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-26 19:18 Yang Shi
2024-06-28 16:54 ` Catalin Marinas
2024-06-28 16:57   ` Christoph Lameter (Ampere)
2024-06-28 17:24     ` Catalin Marinas
2024-06-28 18:20       ` Yang Shi
2024-07-01 19:43         ` Catalin Marinas
2024-07-02 10:26           ` Ryan Roberts
2024-07-02 11:22             ` David Hildenbrand
2024-07-02 12:36               ` Ryan Roberts
2024-07-02 12:58                 ` David Hildenbrand
2024-07-02 13:26                   ` Ryan Roberts
2024-07-02 13:50                     ` David Hildenbrand
2024-07-02 14:51                       ` Ryan Roberts
2024-07-15 13:09             ` Ryan Roberts
2024-07-02 22:21           ` Yang Shi
2024-07-04 10:03             ` Catalin Marinas
2024-07-05 17:05               ` Christoph Lameter (Ampere)
2024-07-05 18:24                 ` Catalin Marinas
2024-07-05 18:51                   ` Christoph Lameter (Ampere)
2024-07-06  9:47                     ` Catalin Marinas
2024-07-09 17:56               ` Yang Shi
2024-07-09 18:35                 ` Catalin Marinas
2024-07-09 22:29                   ` Yang Shi [this message]
2024-07-10  9:22                     ` Catalin Marinas
2024-07-10 18:43                       ` Yang Shi
2024-07-11 17:43                         ` Catalin Marinas
2024-07-11 18:17                           ` Yang Shi
2024-08-13 17:09                             ` Yang Shi
2024-08-21 10:18                             ` Catalin Marinas
2024-08-21 11:32                               ` Dev Jain
2024-08-23  9:59                               ` Will Deacon
2024-06-28 18:26       ` Christoph Lameter (Ampere)

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