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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: RKwVJxEXcqAzvfxwDJVZ3mkyAXZyR_D4 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjEyMDA3MiBTYWx0ZWRfX/RivLk73Qelo MffAz9ZydOneUGjGjA4j2JqDjxsy86ZALXUqasmtIINloqzVPz057WxJNGG9POwtl+ejnhkfJOZ q8kD7JULuhjNXDvRG254K+uG4bXYoTs= X-Proofpoint-ORIG-GUID: RKwVJxEXcqAzvfxwDJVZ3mkyAXZyR_D4 X-Authority-Analysis: v=2.4 cv=N94Z0W9B c=1 sm=1 tr=0 ts=6a2bbe7b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=DVNErGSwdtF8OHn2hLoakQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=mUgSyTONyoZcvpXPCScA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEyMDA3MiBTYWx0ZWRfX6EpjLGBP6RyM Np5jzGPhhGjSB19JiezCaR6j6cipmSEG8RFZNw0Pc/s/1+Gw7dafmV7bF9ia3d3Lv5doXOqE22O NM4m2xDet79eHIMYq4GJqVygKQ5l6d6EBDtlg9BqOFOzPhwrUssLmO6KU3NIMAzyRb/ZThCBz2y BRnGPzQE/dHHbexmKZH5giPk5Z5tVoeDWwkp7fSLDtskklJFeacr2ITnhd3aFwe5tJ/BY4jzvA9 tl50idxSUJVik9ZvvqO5S/j//tUxcWr4P5G+3fiZGXEuqcT0gbmOxYGHPbEn/R3i6l7qNhPOZqK EG55N0kZ+55WLCA2kmupE5tHf9wl/mAeKtIMeeuoqFOPj/5Rf3uHm143DkEVbATLWMVPgbVeEtQ zIaQBraQQdDZ4qiB0+9fUPtBfJ3SZgGdFYZwwM14RxLErifGbFnaicEod/4u1bWgtuPIIRjNOk7 dJNCh+dBKtU0woh4nVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-12_01,2026-06-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606120072 On 6/11/2026 9:52 PM, Kathiravan Thirumoorthy wrote: > > On 6/11/2026 4:45 PM, Vinod Koul wrote: >> On 02-06-26, 14:40, Kathiravan Thirumoorthy wrote: >>> Qualcomm's IPQ9650 SoC has 3 Gen3 dual lane and 2 Gen3 single lane >>> controllers with the QMP PHYs. Unlike the PHYs in the other IPQ SoC, >>> refgen supply is needed to bringup the PHYs. Both single and dual lane >>> shares the same HW init sequence. So reuse the tables. >>> >>> Document the compatible along with refgen supply and add the phy driver >>> support for it. >> Please rebase this on phy-next tomorrow. It does not apply for me due to >> changes applied ealier today > > There is a discussion open about the supplies[1]. Once that is > clarified, let me re spin. So we can take up this series for v7.3 once > that discussion is closed. > > [1] > https://lore.kernel.org/linux-arm-msm/aiqYtowP2DQt7Jw0@vaman/T/#m37a571fac0c77fd00f6379ad9a2414b60431820b > Discussion is concluded and I have sent the V2[1] on top of phy-next (2ace2e949979 ("phy: rockchip: inno-usb2: Add missing clkout_ctl_phy kerneldoc")). Please take a look at it. [1] https://lore.kernel.org/linux-arm-msm/20260612-ipq9650_pcie_phy-v2-0-b938cc2fc267@qti.qualcomm.com/#t