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([2a09:80c0:192:0:5dac:bf3d:c41:c3e7]) by smtp.gmail.com with ESMTPSA id y19-20020a05600c365300b003fa8dbb7b5dsm12475267wmq.25.2023.06.29.04.22.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jun 2023 04:22:09 -0700 (PDT) Message-ID: Date: Thu, 29 Jun 2023 13:22:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v12 04/22] x86/cpu: Detect TDX partial write machine check erratum To: Kai Huang , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, x86@kernel.org, dave.hansen@intel.com, kirill.shutemov@linux.intel.com, tony.luck@intel.com, peterz@infradead.org, tglx@linutronix.de, bp@alien8.de, mingo@redhat.com, hpa@zytor.com, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, ashok.raj@intel.com, reinette.chatre@intel.com, len.brown@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, ying.huang@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, nik.borisov@suse.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com References: <0f701502157029989617bcb3f5940ff48e19a2b2.1687784645.git.kai.huang@intel.com> Content-Language: en-US From: David Hildenbrand Organization: Red Hat In-Reply-To: <0f701502157029989617bcb3f5940ff48e19a2b2.1687784645.git.kai.huang@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 26.06.23 16:12, Kai Huang wrote: > TDX memory has integrity and confidentiality protections. Violations of > this integrity protection are supposed to only affect TDX operations and > are never supposed to affect the host kernel itself. In other words, > the host kernel should never, itself, see machine checks induced by the > TDX integrity hardware. > > Alas, the first few generations of TDX hardware have an erratum. A > partial write to a TDX private memory cacheline will silently "poison" > the line. Subsequent reads will consume the poison and generate a > machine check. According to the TDX hardware spec, neither of these > things should have happened. > > Virtually all kernel memory accesses operations happen in full > cachelines. In practice, writing a "byte" of memory usually reads a 64 > byte cacheline of memory, modifies it, then writes the whole line back. > Those operations do not trigger this problem. > > This problem is triggered by "partial" writes where a write transaction > of less than cacheline lands at the memory controller. The CPU does > these via non-temporal write instructions (like MOVNTI), or through > UC/WC memory mappings. The issue can also be triggered away from the > CPU by devices doing partial writes via DMA. > > With this erratum, there are additional things need to be done. Similar > to other CPU bugs, use a CPU bug bit to indicate this erratum, and > detect this erratum during early boot. Note this bug reflects the > hardware thus it is detected regardless of whether the kernel is built > with TDX support or not. > > Signed-off-by: Kai Huang > Reviewed-by: Kirill A. Shutemov > --- Reviewed-by: David Hildenbrand -- Cheers, David / dhildenb