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Sat, 31 Oct 2026 03:20:16 -0700 (PDT) Received: from [192.168.29.63] ([49.43.230.158]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1ac19f4b08bsm16523200c88.16.2026.10.31.03.20.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 31 Oct 2026 03:20:16 -0700 (PDT) Message-ID: Date: Sat, 31 Oct 2026 15:50:09 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Krishna Chaitanya Chundru Subject: Re: [PATCH RFC v3 3/5] arm64: dts: qcom: nord-ride-embedded: Enable PCIe controllers and PHY To: Shawn Guo Cc: Konrad Dybcio , Rob Herring , Bjorn Andersson , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Yu Zhang , Shuai Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bartosz Golaszewski References: <20261021022921.2053957-1-shengchao.guo@oss.qualcomm.com> <20261021022921.2053957-4-shengchao.guo@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <20261021022921.2053957-4-shengchao.guo@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: jVgRosxvvF_3XvusQ_lxoaSKnAsnKemt X-Proofpoint-ORIG-GUID: jVgRosxvvF_3XvusQ_lxoaSKnAsnKemt X-Authority-Analysis: v=2.4 cv=S5RMU4sP c=1 sm=1 tr=0 ts=6ae5c0e2 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=16YkeKhe4TlTIPRGKl4Ycg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=GcTTplM3uHFL1Q-H_JYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDMxMDA0MSBTYWx0ZWRfX2ftq17fNwuzx oyIv6hiGo74xFH8JkFFh9TGjCDpqnTK+85gyPfcXgsMKSn+yQzzm0URSdaMXH/NdKb/0IYyTWOM XXu8lTaxvZf/+V8qbdVUTiZhAQG5aac= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDMxMDA0MSBTYWx0ZWRfX7tthO8dO0BxX vf3WmojJEWL7A8oV05LXF88kdgfkw7zIR7n9nEbTsmYF3fEgOz2p76fV7t2ksI96teJfBs7bQTl vzs8SNyeAySsW+yYCfxpD5Mhl8rtHRIIslpFts4DWPfHGgcUFOMauHVcY0HQeav3ibV0Y+6Dh8O M72pWSKPnQyyBoBVmGvNRO7ZXStzetm1Y51rzujSn5X7Q5BL6vrEV7RqVM0dCAMnalZitj+x0o9 /Z8/qaVN9XAFIXU0XA3dYpG1Nnomrx54vdJ+Ss9rEzz7S2pMM0n/0HD7LJt3QAERA5RNMJ9bP8l ieH2KqLEttc5TB6xEVFAb3CKaH0r01SLYlTtfjnoVh2GLX3sKhtKmdKV5PMv1ZZLaAywFSlyekV BLzBgGTHhhDSGHRKsLpexINjQdb6IA7mDSrRAYWJa5Y+OQk8lu/OY0DtN+VbU21vQUcfq1BPM3u IQknLBU1EqSGuQINLKA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-31_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2610310041 On 10/21/2026 7:59 AM, Shawn Guo wrote: > From: Krishna Chaitanya Chundru > > The Nord Ride Embedded board routes all four PCIe links, so enable > pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and > describe the PERST# and WAKE# lines of each root port. > > Signed-off-by: Krishna Chaitanya Chundru > Reviewed-by: Konrad Dybcio > Reviewed-by: Abel Vesa > Reviewed-by: Bartosz Golaszewski > Signed-off-by: Shawn Guo > --- > .../boot/dts/qcom/nord-ride-embedded.dts | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > index 49635695f832..fcc07226db8b 100644 > --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > @@ -366,6 +366,55 @@ vreg_l3l_1p8: ldo3 { > }; > }; > > +&pcie_phy { > + vdda-phy-a-supply = <&vreg_l6a_1p2>; > + vdda-phy-b-supply = <&vreg_l4a_1p2>; > + vdda-phy-c-supply = <&vreg_l4a_1p2>; > + vdda-phy-d-supply = <&vreg_l4a_1p2>; > + vdda-pll-a-supply = <&vreg_l1e_0p9>; Hi Shawn, I did a mistake while sharing these changes, pll supply for b, c, d should be l2e instead of l1e. -    vdda-pll-b-supply = <&vreg_l1e_0p9>; -    vdda-pll-c-supply = <&vreg_l1e_0p9>; -    vdda-pll-d-supply = <&vreg_l1e_0p9>; +    vdda-pll-b-supply = <&vreg_l2e_0p9>; +    vdda-pll-c-supply = <&vreg_l2e_0p9>; +    vdda-pll-d-supply = <&vreg_l2e_0p9>; Can you update them as this patch is not applied yet. - Krishna Chaitanya. > + vdda-pll-b-supply = <&vreg_l1e_0p9>; > + vdda-pll-c-supply = <&vreg_l1e_0p9>; > + vdda-pll-d-supply = <&vreg_l1e_0p9>; > + > + status = "okay"; > +}; > + > +&pcie0 { > + status = "okay"; > +}; > + > +&pcie0_port0 { > + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; > +}; > + > +&pcie1 { > + status = "okay"; > +}; > + > +&pcie1_port0 { > + reset-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; > +}; > + > +&pcie2 { > + status = "okay"; > +}; > + > +&pcie2_port0 { > + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; > +}; > + > +&pcie3 { > + status = "okay"; > +}; > + > +&pcie3_port0 { > + reset-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; > +}; > + > &qupv3_0 { > firmware-name = "qcom/nord/qupv3fw.elf"; >