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From: Zicheng Qu <quzicheng@huawei.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <lars@metafoo.de>,
	<mturquette@linaro.org>, <linux-clk@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Cc: <tanghui20@huawei.com>, <zhangqiao22@huawei.com>,
	<judy.chenhui@huawei.com>, <quzicheng@huawei.com>
Subject: Re: [PATCH] clk: clk-axi-clkgen: fix division by zero in axi_clkgen_calc_params()
Date: Thu, 7 Nov 2024 21:45:59 +0800	[thread overview]
Message-ID: <cb94d71e-d421-4781-adf1-301da10f4d6a@huawei.com> (raw)
In-Reply-To: <20241026072344.976154-1-quzicheng@huawei.com>

Gentle ping.

On 2024/10/26 15:23, Zicheng Qu wrote:
> In the axi_clkgen_set_rate() function, parameters fin and fout are
> checked in advance to ensure they are not equal to zero. However, in the
> axi_clkgen_calc_params() function, they might become zero after /= 1000.
> This could lead to a division by zero error when calculating
> fvco_max_fract * d_max / fin or DIV_ROUND_CLOSEST(fvco, fout). The same
> issue occurs in the axi_clkgen_determine_rate() function, where there
> is no check to ensure they are non-zero.
>
> Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Zicheng Qu <quzicheng@huawei.com>
> ---
>   drivers/clk/clk-axi-clkgen.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
> index bf4d8ddc93ae..369b15a2660e 100644
> --- a/drivers/clk/clk-axi-clkgen.c
> +++ b/drivers/clk/clk-axi-clkgen.c
> @@ -344,7 +344,7 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
>   	uint32_t filter;
>   	uint32_t lock;
>   
> -	if (parent_rate == 0 || rate == 0)
> +	if (parent_rate < 1000 || rate < 1000)
>   		return -EINVAL;
>   
>   	axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
> @@ -392,6 +392,9 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw,
>   	unsigned int d, m, dout;
>   	unsigned long long tmp;
>   
> +	if (req->best_parent_rate < 1000 || req->rate < 1000)
> +		return -EINVAL;
> +
>   	axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,
>   			       &d, &m, &dout);
>   

      parent reply	other threads:[~2024-11-07 13:46 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-26  7:23 Zicheng Qu
2024-10-31 13:50 ` Zicheng Qu
2024-11-07 13:45 ` Zicheng Qu [this message]

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