From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44E4DC47255 for ; Mon, 11 May 2020 12:25:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A5D52080C for ; Mon, 11 May 2020 12:25:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729872AbgEKMZy (ORCPT ); Mon, 11 May 2020 08:25:54 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4389 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729763AbgEKMZs (ORCPT ); Mon, 11 May 2020 08:25:48 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 009F7FA603E696F8AFB2; Mon, 11 May 2020 20:25:43 +0800 (CST) Received: from [127.0.0.1] (10.173.220.25) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Mon, 11 May 2020 20:25:32 +0800 Subject: Re: [RFC PATCH v3 1/2] arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature To: Mark Rutland CC: , , , , , , , , , , , , , , , References: <20200414112835.1121-1-yezhenyu2@huawei.com> <20200414112835.1121-2-yezhenyu2@huawei.com> <20200505101405.GB82424@C02TD0UTHF1T.local> From: Zhenyu Ye Message-ID: Date: Mon, 11 May 2020 20:25:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20200505101405.GB82424@C02TD0UTHF1T.local> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2020/5/5 18:14, Mark Rutland wrote: > On Tue, Apr 14, 2020 at 07:28:34PM +0800, Zhenyu Ye wrote: >> ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a >> range of input addresses. This patch detect this feature. >> >> Signed-off-by: Zhenyu Ye >> --- >> arch/arm64/include/asm/cpucaps.h | 3 ++- >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 11 +++++++++++ >> 3 files changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h >> index 8eb5a088ae65..950095a72617 100644 >> --- a/arch/arm64/include/asm/cpucaps.h >> +++ b/arch/arm64/include/asm/cpucaps.h >> @@ -61,7 +61,8 @@ >> #define ARM64_HAS_AMU_EXTN 51 >> #define ARM64_HAS_ADDRESS_AUTH 52 >> #define ARM64_HAS_GENERIC_AUTH 53 >> +#define ARM64_HAS_TLBI_RANGE 54 >> >> -#define ARM64_NCAPS 54 >> +#define ARM64_NCAPS 55 >> >> #endif /* __ASM_CPUCAPS_H */ >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index ebc622432831..ac1b98650234 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -592,6 +592,7 @@ >> >> /* id_aa64isar0 */ >> #define ID_AA64ISAR0_RNDR_SHIFT 60 >> +#define ID_AA64ISAR0_TLBI_RANGE_SHIFT 56 >> #define ID_AA64ISAR0_TS_SHIFT 52 >> #define ID_AA64ISAR0_FHM_SHIFT 48 >> #define ID_AA64ISAR0_DP_SHIFT 44 >> @@ -605,6 +606,9 @@ >> #define ID_AA64ISAR0_SHA1_SHIFT 8 >> #define ID_AA64ISAR0_AES_SHIFT 4 >> >> +#define ID_AA64ISAR0_TLBI_RANGE_NI 0x0 >> +#define ID_AA64ISAR0_TLBI_RANGE 0x2 >> + >> /* id_aa64isar1 */ >> #define ID_AA64ISAR1_I8MM_SHIFT 52 >> #define ID_AA64ISAR1_DGH_SHIFT 48 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 9fac745aa7bb..31bcfd0722b5 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -124,6 +124,7 @@ static bool __system_matches_cap(unsigned int n); >> */ >> static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { >> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLBI_RANGE_SHIFT, 4, 0), > > This should be FTR_HIDDEN as userspace has no reason to see this. > > Otherwise this all seems to match the ARM ARM. > > Mark. > OK, I will change it to FTR_HIDDEN in next version series. Thanks, Zhenyu