From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759572AbcHEIfi (ORCPT ); Fri, 5 Aug 2016 04:35:38 -0400 Received: from regular1.263xmail.com ([211.150.99.135]:37603 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756024AbcHEIfR (ORCPT ); Fri, 5 Aug 2016 04:35:17 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: frank.wang@rock-chips.com X-FST-TO: frank.wang@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: frank.wang@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Frank Wang Subject: Re: [PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 To: =?UTF-8?Q?Heiko_St=c3=bcbner?= , Xing Zheng References: <1470122401-31934-1-git-send-email-zhengxing@rock-chips.com> <1470122401-31934-3-git-send-email-zhengxing@rock-chips.com> <1918977.W0kRfKbZsD@diego> Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org, briannorris@chromium.org, huangtao@rock-chips.com, zhangqing@rock-chips.com, wulf@rock-chips.com, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, daniel.meng@rock-chips.com, frank.wang@rock-chips.com Message-ID: Date: Fri, 5 Aug 2016 16:34:42 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <1918977.W0kRfKbZsD@diego> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko, On 2016/8/5 3:10, Heiko Stübner wrote: > Hi Xing, > > Am Dienstag, 2. August 2016, 15:19:56 schrieb Xing Zheng: >> Export these source clocks for usbphy. >> >> Signed-off-by: Xing Zheng > can you please provide a rationale why you need manual control over that > intermediate clock? Well, From below graph, you can see that 'clk_usbphyX_480m' is generated from usb2phy, and 'clk_usbphy_480m' which select from clk_usbphyX_480m_src via a gate (G13[12]) provided 480M clock to other modules. xin24m |__ clk_usb2phy0_ref | |__ clk_usbphy0_480m | |__clk_usbphy0_480m_src | |__clk_usbphy_480m | |__ ... ... |__ clk_usb2phy1_ref |__ clk_usbphy1_480m |__clk_usbphy1_480m_src > The two usbphys seem to use the clk_usb2phyX_ref clocks, generate the 480m > clocks, but do not seem to need the clk_usbphyX_480m_src gates. Yeah, they used to be. However, the story went something like this, Some PM suspend process related ehci/ohci controller are base on 480m clocks, unfortunately, usb2-phy suspended earlier than ehci/ohci (usb2-phy will be auto suspended if no devices plug-in), and the clk-480m provided by it was disabled if no module used. As a result, the PM suspend process was blocked when it run into ehci/ohci module. Hence, we are planing to refer clk_usbphyX_480m_src into each ehci/ohci driver. Maybe you will challenge why not refer clk_usbphy_480m directly? because there are two ehci/ohci connected in the different usb2phy, and only one clk_usbphy_480m clock was selected in clock tree. BR. Frank > The clk_usbphyX_480m_src clocks on the other hand only lead to the > clk_usbphy_480m mux, so I'd like some explanation on what you want to achieve > here :-) > > > Thanks > Heiko >