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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c5edf251a6csm17465094a12.13.2026.01.22.06.00.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jan 2026 06:00:26 -0800 (PST) Message-ID: Date: Thu, 22 Jan 2026 19:30:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260122-upstream_v3_glymur_introduction-v5-0-8ba76c354e9a@oss.qualcomm.com> <20260122-upstream_v3_glymur_introduction-v5-3-8ba76c354e9a@oss.qualcomm.com> Content-Language: en-US From: Pankaj Patil In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 93KefNL-J8_Ebr59KPOMSdZRREODHNwZ X-Authority-Analysis: v=2.4 cv=N7ck1m9B c=1 sm=1 tr=0 ts=69722d7d cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=XrNrwu1fJH_fsFYXVS4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 93KefNL-J8_Ebr59KPOMSdZRREODHNwZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDEwNiBTYWx0ZWRfX+U7Rye8ms6eP tIb0+6bvfFy9+5DbgY1pOmhdB8mX7kW9Azt6qPBwJS47dNw+rm8enD420Uz5X+qvlYxps0VTM9A rLH8b8sluSn3ksXO3NF7JfOPIYSXCWtGEplqAHsndxU2EQksqq28ddcz3BIvuzSh2nPf3Y0nEmc 6sJ2Bf7Q2+KKxZXJuOm9su5j6ygbNzEIyvTWhtbg6UEZ2efQh3Mafqt/AT+Ab/V8/zTDh3TCtz2 qhEuJnUN8Qsexr339mLlAuyUcXAFlpZCV0O8k1GBruyFP9eViW17GaI9fz2sxxnGJFaA8jqCp8o 4qeSe+xMLmUAnDtAEyIV0VIYwoVsjnDrd+21LRqDIdVprHIqYduI7TdKb2PcDZR4+n7Xt/AzAYk PoLx/Il1jHS/bfXVvMKqrYH0Ngv5I04Clek9ELzTERjkGFRVlB1mapW/Vx55uXXcer4iI5UTEh4 2R1JY1QvXptqIS5AbLA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_01,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220106 On 1/22/2026 4:11 PM, Dmitry Baryshkov wrote: > On Thu, Jan 22, 2026 at 12:15:17PM +0530, Pankaj Patil wrote: >> On 1/22/2026 6:52 AM, Dmitry Baryshkov wrote: >>> On Thu, Jan 22, 2026 at 12:05:13AM +0530, Pankaj Patil wrote: >>>> Introduce the base device tree support for Glymur – Qualcomm's >>>> next-generation compute SoC. The new glymur.dtsi describes the core SoC >>>> components, including: >>>> >>>> - CPUs and CPU topology >>>> - Interrupt controller and TLMM >>>> - GCC,DISPCC and RPMHCC clock controllers >>>> - Reserved memory and interconnects >>>> - APPS and PCIe SMMU and firmware SCM >>>> - Watchdog, RPMHPD, APPS RSC and SRAM >>>> - PSCI and PMU nodes >>>> - QUPv3 serial engines >>>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >>>> - PDP0 mailbox, IPCC and AOSS >>>> - Display clock controller >>>> - SPMI PMIC arbiter with SPMI0/1/2 buses >>>> - SMP2P nodes >>>> - TSENS and thermal zones (8 instances, 92 sensors) >>>> >>>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >>>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur >>>> >>>> Enabled PCIe controllers and associated PHY to support boot to >>>> shell with nvme storage, >>>> List of PCIe instances enabled: >>>> >>>> - PCIe3b >>>> - PCIe4 >>>> - PCIe5 >>>> - PCIe6 >>>> >>>> Co-developed-by: Jyothi Kumar Seerapu >>>> Signed-off-by: Jyothi Kumar Seerapu >>>> Co-developed-by: Maulik Shah >>>> Signed-off-by: Maulik Shah >>>> Co-developed-by: Sibi Sankar >>>> Signed-off-by: Sibi Sankar >>>> Co-developed-by: Taniya Das >>>> Signed-off-by: Taniya Das >>>> Co-developed-by: Kamal Wadhwa >>>> Signed-off-by: Kamal Wadhwa >>>> Co-developed-by: Qiang Yu >>>> Signed-off-by: Qiang Yu >>>> Co-developed-by: Abel Vesa >>>> Signed-off-by: Abel Vesa >>>> Co-developed-by: Manaf Meethalavalappu Pallikunhi >>>> Signed-off-by: Manaf Meethalavalappu Pallikunhi >>>> Co-developed-by: Jishnu Prakash >>>> Signed-off-by: Jishnu Prakash >>>> Signed-off-by: Pankaj Patil >>>> --- >>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 6122 ++++++++++++++++++++++++++ >>>> arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 107 + >>>> arch/arm64/boot/dts/qcom/pmh0101.dtsi | 45 + >>>> arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 83 + >>>> arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 83 + >>>> arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + >>>> arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + >>>> 7 files changed, 6555 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> new file mode 100644 >>>> index 000000000000..c0ecc64202c7 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >>>> + >>>> + pmh0101-thermal { >>> >>> Why do we have PMIC thermal zones as a part of SoC DTSI? >> >> There were comments on v3 about moving them to out of board dts, >> https://lore.kernel.org/all/aUko20ORsgrlZrIn@linaro.org/ >> glymur-pmics.dtsi was dropped in v4, the changes were moved to glymur.dtsi > > Anyway, the PMICS (nor their thermal zones) are not a part of the SoC. > As such, they don't belong to glymur.dtsi. > Moving pmic thermal zones to their respective pmic dtsi files in next revision