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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDEzNCBTYWx0ZWRfX3Tt/JnTRSUmA vXaG516tRpDmsqTwVnhULU5oKGbKJ0OdKyJc5pv2D848ZPC1wrSMtFPMGZPJG+fAoOKd45Nz0pb v4ASOhFhAs/U3c1L5bobpj02MLTO1xA= X-Authority-Analysis: v=2.4 cv=UYBhjqSN c=1 sm=1 tr=0 ts=6a67652a cx=c_pps a=z9lCQkyTxNhZyzAvolXo/A==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=kF0Kh6n4e_L3U_yLb1EA:9 a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 X-Proofpoint-GUID: 3lJ3BlpxYu9GRgztr5gZJxbAfGFpxdVp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDEzNCBTYWx0ZWRfX4CTd4ScaARvG kWWY5Z2tGUAzjolvXyL1ORkS4rJClGXANWQEM53rjYB9W2VXueJjY/x7TJyNoQzx5n74/cZh8E2 XtFXwFErZVBsITC+MtwjQGv0EdUgiBcSEpNqucpP/Sfg36FnTR2zpiCuYSv8uj22xaPkXkxdb3r 0Den2249xHvkziX87I31HcJyiRiZ8ZVDFmZ+Lbph7OzgJ9y6PBFsoilcSXTbN4MjaVRdpdQPRgx GqjJyZxkx1VGfMXNJvOIy6VofHe+KY3U/FpGQTvqbLxvzomYrNOYfpMnr86DOTtdYPBCPVSsmMj xIWnRzCkXpRGr3EJyN+Adrxe42wKl/S5lBX6sGkE6tobAsvdpTDoGUX2RDN1v03AqVlHYBZ+D8v AYOUVRM/sn69FZTdDXR1+5qUC/1lNgCdr9cOUqQaowQjiMrtX3Ix9narHaFZS7CCpcknZ7KYHSF J+nzMj9+g8yzPyJ7MMg== X-Proofpoint-ORIG-GUID: 3lJ3BlpxYu9GRgztr5gZJxbAfGFpxdVp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_04,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270134 On 7/24/26 12:01 PM, Qiang Yu wrote: > Add the PCIe3 PHY and the PCIe3a controller nodes. PCIe3a and PCIe3b share > a single Gen5x8 QMP PHY that can be configured either as one x8 link or as > two independent x4 links (bifurcated). > > The shared PHY is modelled as a single pcie3_phy provider; each controller > selects its sub-PHY through &pcie3_phy (index 0 for PCIe3a, index 1 for > PCIe3b). Update the GCC pipe clock parent array to reference the new PHY's > clock outputs instead of the placeholders. > > Signed-off-by: Qiang Yu > --- Reviewed-by: Konrad Dybcio Konrad