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Thu, 10 Sep 2026 16:17:33 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v4 10/15] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Date: Thu, 10 Sep 2026 16:17:02 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A893:EE_|CYXPR12MB9277:EE_ X-MS-Office365-Filtering-Correlation-Id: ba84a20d-f378-4a8d-b8a9-08df0f91be08 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|23010399003|1800799024|36860700016|10067099003|56012099006|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CLH4ryewxEIpbxohRp+nO10mpNqjvJISNCwunHN849TTwFWz7UGHTKrOTXOooPLbVZUYwiqkat817SgTyV4JZ9zEDYCaZKO37mH6nvou/Yk9Ic62n3j6e4MtCSEmvLgPDiDKSdYlhgsg06glCPst0fqahgG9l7Kwz5VQd7K6S6+YaI44EV+2P1URnC9g07gtYDvWLRhB5bV1z46yUvaCPSTOn3X68s/PiRcMYfxKjHX0V8SjwEoaR+IBZEbX8DfKX9Jz2cPFkeXdgVICdCOXNQwJSDeWU97htv+9uKG7aQXDCfvJYrJQvDCuXlHIAmRSZgscwbzAiOVdL2y01+5w+cOyuHagJ/RqkcaY+buLjBg+CYU+oOPaLj9D3eeT+GaHNOgyOJ/+kgeipR3h/oGuUbrbziIEaySsDTTysl7VowyYbeLfxih+8cYyODcpRJib X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 23:17:54.0904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba84a20d-f378-4a8d-b8a9-08df0f91be08 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A893.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9277 For a PRI-enabled master, convert every PRIQ entry into an iopf_fault and report it through iommu_report_device_fault(). For an unknown StreamID or a master without PRI enabled, keep the existing LAST-page DENY path. Merge its two messages into one ratelimited line so a faulty device cannot flood the kernel log. Discard any PASID Stop Marker (LRW = 0b100) prior to the fault report and the DENY fallback both, because a Stop Marker does not expect a response. The IOPF infrastructure requires the driver to discard it, as per the doc at iommu_report_device_fault(). This also matches the intel-iommu code. Note that master->pri_enabled will only be set by a later change, once all the PRI paths are ready. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 43a6029cef430..c631c6344685d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2370,6 +2370,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) { + struct arm_smmu_master *master; u32 sid, ssid; u16 grpid; bool ssv, last; @@ -2380,9 +2381,47 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) last = FIELD_GET(PRIQ_0_PRG_LAST, evt[0]); grpid = FIELD_GET(PRIQ_1_PRG_IDX, evt[1]); - dev_info(smmu->dev, "unexpected PRI request received:\n"); - dev_info(smmu->dev, - "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", + /* + * A PASID Stop Marker (LRW = 0b100) does not expect a response and + * must be discarded before fault reporting: see the documentation + * at iommu_report_device_fault(). + */ + if (last && !(evt[0] & (PRIQ_0_PERM_READ | PRIQ_0_PERM_WRITE))) + return; + + mutex_lock(&smmu->streams_mutex); + master = arm_smmu_find_master(smmu, sid); + if (master && master->pri_enabled) { + struct iopf_fault iopf_fault = {}; + struct iommu_fault *fault = &iopf_fault.fault; + + fault->type = IOMMU_FAULT_PAGE_REQ; + if (last) + fault->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (ssv) { + fault->prm.flags |= + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + fault->prm.pasid = ssid; + } + fault->prm.grpid = grpid; + if (evt[0] & PRIQ_0_PERM_READ) + fault->prm.perm |= IOMMU_FAULT_PERM_READ; + if (evt[0] & PRIQ_0_PERM_WRITE) + fault->prm.perm |= IOMMU_FAULT_PERM_WRITE; + if (evt[0] & PRIQ_0_PERM_EXEC) + fault->prm.perm |= IOMMU_FAULT_PERM_EXEC; + if (evt[0] & PRIQ_0_PERM_PRIV) + fault->prm.perm |= IOMMU_FAULT_PERM_PRIV; + fault->prm.addr = FIELD_GET(PRIQ_1_ADDR_MASK, evt[1]) << 12; + + iommu_report_device_fault(master->dev, &iopf_fault); + mutex_unlock(&smmu->streams_mutex); + return; + } + mutex_unlock(&smmu->streams_mutex); + + dev_info_ratelimited(smmu->dev, + "unexpected PRI request: sid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", sid, ssid, grpid, last ? "L" : "", evt[0] & PRIQ_0_PERM_PRIV ? "" : "un", evt[0] & PRIQ_0_PERM_READ ? "R" : "", -- 2.43.0