Re: [PATCH v7 1/2] arm64: dts: intel: agilex5: add USB3.1 controller node

[Krzysztof Kozlowski <krzk@kernel.org>]

On 11/09/2026 11:09, adrian.ho.yin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> 
> Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
> Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
> = 2) to match the USB DMA address width of the interconnect. Enable it in
> host mode on the SoCDK board.
> 
> ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
> same hardware clock source on this SoC.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++
>  .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  5 +++
>  2 files changed, 40 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index f54767d1526e..523f722a2a64 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -493,6 +493,41 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		usb31_bus: usb-bus@11000000 {

No, USB bus is not a simple bus. You probably wanted simple bus or any
other approved, but not discouraged names from simple-bus.

Don't come up with own naming.


Best regards,
Krzysztof