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From: Mikko Perttunen <cyndis@kapsi.fi>
To: Thierry Reding <thierry.reding@gmail.com>,
	Mikko Perttunen <mperttunen@nvidia.com>
Cc: rjw@rjwysocki.net, viresh.kumar@linaro.org, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster
Date: Mon, 3 Apr 2017 18:18:43 +0300	[thread overview]
Message-ID: <cc23f916-ea17-94b7-abb1-a77d776b0b28@kapsi.fi> (raw)
In-Reply-To: <20170403140617.GA22966@ulmo.ba.sec>

On 04/03/2017 05:06 PM, Thierry Reding wrote:
> On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote:
>> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
>> registers that initiate CPU frequency/voltage transitions.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> ---
>>  .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt   | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
>> new file mode 100644
>> index 000000000000..50cd615219e9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
>> @@ -0,0 +1,22 @@
>> +NVIDIA Tegra CCPLEX_CLUSTER area
>> +
>> +Required properties:
>> +- compatible: Should contain one of the following:
>> +  - "nvidia,tegra186-ccplex-cluster": for Tegra186
>> +- reg: Must contain an (offset, length) pair of the register set for each
>> +  entry in reg-names.
>> +- reg-names: Must include the following entries:
>> +  - "a57": Public aperture for A57 CPU cluster
>> +  - "denver": Public aperture for Denver CPU cluster
>> +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables
>
> "phandle"

Will fix.

>
>> +Example:
>> +
>> +	ccplex@e000000 {
>> +		compatible = "nvidia,tegra186-ccplex-cluster";
>> +		reg = <0x0 0x0e060000 0x0 0x1000>,
>> +		      <0x0 0x0e070000 0x0 0x1000>;
>> +		reg-names = "a57", "denver";
>> +
>> +		nvidia,bpmp = <&bpmp>;
>> +	};
>
> Where's the information about the register offsets coming from? The TRM
> says that CCPLEX_CLUSTER has a single aperture from 0x0e000000 to
> 0x0e3fffff.

Some internal document with a name related to Denver power management, 
IIRC. I'll link it to you tomorrow.

>
> Thierry
>

  reply	other threads:[~2017-04-03 15:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-03 12:42 [PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver Mikko Perttunen
2017-04-03 12:42 ` [PATCH 2/3] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Mikko Perttunen
2017-04-03 14:06   ` Thierry Reding
2017-04-03 15:18     ` Mikko Perttunen [this message]
2017-04-03 14:24   ` Jon Hunter
2017-04-03 15:19     ` Mikko Perttunen
2017-04-03 12:42 ` [PATCH 3/3] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Mikko Perttunen
2017-04-03 14:47 ` [PATCH 1/3] cpufreq: Add Tegra186 cpufreq driver Thierry Reding
2017-04-03 15:38   ` Mikko Perttunen

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