From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751766AbdE3OQA (ORCPT ); Tue, 30 May 2017 10:16:00 -0400 Received: from foss.arm.com ([217.140.101.70]:59586 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751127AbdE3OP7 (ORCPT ); Tue, 30 May 2017 10:15:59 -0400 Subject: Re: [PATCH 0/6] Add support for the ICU unit in Marvell Armada 7K/8K To: Thomas Petazzoni , Thomas Gleixner , Jason Cooper , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement References: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org, Nadav Haklai , Hanna Hawa , Yehuda Yitschak , Antoine Tenart From: Marc Zyngier Organization: ARM Ltd Message-ID: Date: Tue, 30 May 2017 15:15:54 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thomas, On 30/05/17 10:16, Thomas Petazzoni wrote: > Hello, > > The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which > contains the CPU cores) and the CP (which contains most > peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs, > doubling the number of available peripherals. > > In terms of interrupt handling, all devices in the CPs are connected > through wired interrupt to a unit called ICU located in each CP. This > unit converts the wired interrupts from the devices into memory > transactions. > > Inside the AP, there is a GIC extension called GICP, which allows a > memory write transaction to trigger a GIC SPI interrupt. The ICUs in > each CP are therefore configured to trigger a memory write into the > appropriate GICP register so that a wired interrupt from a CP device > is converted into a memory write, itself converted into a regular GIC > SPI interrupt. > > Until now, the configuration of the ICU was done statically by the > firmware, and therefore the Device Tree files in Linux were specifying > directly GIC interrupts for the interrupts of CP devices. However, > with the growing number of devices in the CP, a static allocation > scheme doesn't work for the long term. > > This patch series therefore makes Linux aware of the ICU: GIC SPI > interrupts are dynamically allocated, and the ICU is configured > accordingly to route a CP wired interrupt to the allocated GIC SPI > interrupt. > > In detail: > > - The first two patches are the Device Tree binding patches > > - The third patch is a minimal driver for the GICP unit. All it does > is clear interrupts that may have been left pending by the > firmware. > > - The fourth patch is the most important done, which adds the driver > for the ICU itself. > > - The fifth patch adjust Kconfig.platforms to select the GICP and ICU > drivers. > > - The last patch adjusts the Device Tree files of the Armada 7K/8K to > use the ICU. For a first drop, this looks quite good, and the few comments I've had should be pretty easy to address. Looking forward to reviewing v2. Thanks, M. -- Jazz is not dead. It just smells funny...