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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-90a8179e4fasm9733956d6.2.2026.08.13.00.44.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Aug 2026 00:45:02 -0700 (PDT) Message-ID: Date: Thu, 13 Aug 2026 15:44:53 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: display: msm: Allow two MDSS power domains To: Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Abel Vesa , Yuanjie Yang , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260720-msm_gdsc2-v1-0-4687866d6cb0@oss.qualcomm.com> <20260720-msm_gdsc2-v1-1-4687866d6cb0@oss.qualcomm.com> Content-Language: en-US From: Yongxing Mou In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YLqvDxGx c=1 sm=1 tr=0 ts=6a7d7607 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=TWG_K1dlhuyH_i5ZZ2cA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEzMDA1MiBTYWx0ZWRfX5i7mAnnGd3d4 LSyUl83wikT7TY2RD2uRAP2rZ55/fZRslO5jsmV6LaPYwzk3EToQCO9VoL4i/tFSNAfQDiqZkh9 cQwQauvVrHtjViB20EOGKWTX478+QIxajPNcQ3XqjUvkr7jfDZnPLYJ2P0xJI4HWNZew5hcvhb8 yv7eAfDnkgwSD+yhqDW+7C9StRyOmsstaXv+mY9UVKeyv06JA3f3vsc+PqC710c3gOjxiBR1Xi2 PqKZgkzRffs/6cuX0yz6WpFFoN0zwN4cGYU8iSPg7nf2wy7aWRBQeG034ooCBywhL3I0PozU60N QhGg3t9/Tx9Bl7GntV8GntaNyzkV14nrmtt46WDn3DJ+y10eARsI93oaqsAel6Kgpizya2B3J5R dTn4+jQN60umTBH5jVuPQJwpxHruVoeCExBugObPMOLlSIPv589alVIuxAKerUttfhGitVQRYE/ 1L449Cv6LfvvB7/AWMA== X-Proofpoint-ORIG-GUID: 6QnbZdGHzcMMbQmXI9dQ2ORvQF8X8obd X-Proofpoint-GUID: 6QnbZdGHzcMMbQmXI9dQ2ORvQF8X8obd X-Proofpoint-Spam-Info: AW1haW4tMjYwODEzMDA1MiBTYWx0ZWRfX5TPvQl9jslJt Ck2eQXqwvqFMs9yQp9iZb1rX+zfQF5fy6WMOiW/qmvlxIhTtA/naIZ0EiR3tBmVGvHuIDw1u/A2 9a4syS6qG6JQBKeTq82Q8KoaKHtT2YI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-13_02,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608130052 On 7/20/2026 4:49 PM, Konrad Dybcio wrote: > On 7/20/26 10:43 AM, Yongxing Mou wrote: >> Kaanapali (SM8750) and Glymur use two display power domains. >> CORE_GDSC powers the main display hardware while INT2_GDSC >> powers a subset of SSPP blocks. > > Can they operate independently? Does INT2_GDSC need to be > powered on after CORE_GDSC? > On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should generally track the same state, except that INT2_GDSC may be powered down when SSPP1 (VIG2/VIG3/DMA5) is unused. - CORE off, INT2 off - CORE on, INT2 off - CORE on, INT2 on > If so, perhaps changing the clock driver to make CORE a parent > of INT2 could be the simpler solution > > Konrad That would still need DT and binding changes -- DPU has to reference INT2_GDSC directly to gate it independently, so it can't be hidden in the clock driver. The two GDSCs have independent GDSCR registers with no HW-enforced sequencing, so they appear to be peers rather than parent/child.