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Fri, 16 Jun 2023 21:19:07 GMT Received: from [10.110.47.14] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 16 Jun 2023 14:18:40 -0700 Message-ID: Date: Fri, 16 Jun 2023 14:18:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 2/3] drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders Content-Language: en-US To: Dmitry Baryshkov , Jessica Zhang , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: , , , References: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> <20230525-add-widebus-support-v1-2-c7069f2efca1@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2iVJ-v10_Juh4txGKOkUWstxCSPb2sqr X-Proofpoint-GUID: 2iVJ-v10_Juh4txGKOkUWstxCSPb2sqr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-16_14,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 mlxlogscore=883 suspectscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306160193 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/14/2023 12:56 AM, Dmitry Baryshkov wrote: > On 14/06/2023 04:57, Jessica Zhang wrote: >> Add a DPU INTF op to set the DATABUS_WIDEN register to enable the >> databus-widen mode datapath. >> >> Signed-off-by: Jessica Zhang >> --- >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |  3 +++ >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c          | 12 ++++++++++++ >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h          |  3 +++ >>   3 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >> index b856c6286c85..124ba96bebda 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c >> @@ -70,6 +70,9 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( >>       if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression) >>           phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf); >> + >> +    if (phys_enc->hw_intf->ops.enable_widebus) >> +        phys_enc->hw_intf->ops.enable_widebus(phys_enc->hw_intf); > > No. Please provide a single function which takes necessary > configuration, including compression and wide_bus_enable. > There are two ways to look at this. Your point is coming from the perspective that its programming the same register but just a different bit. But that will also make it a bit confusing. So lets say the function is called intf_cfg2_xxx(..., bool widebus, bool data_compress) Now for the caller who wants to just enable widebus this will be intf_cfg2_xxx(....., true, false) if we want to do both intf_cfg2_xxx(...., true, true) the last one where we want to do just data_compress(highly unlikely and not recommended) intf_cfg2_xxx(...., false, true) Now someone looking at the code will have to go and find out what each bool is. Whereas with separate ops, its kind of implicit. For that reason, I dont think this patch is bad at all.