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[2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e7f188fsm58134166b.59.2026.04.10.00.59.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Apr 2026 00:59:32 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 08:59:30 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: media: Add bindings for qcom,x1p42100-camss To: Wenmeng Liu , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260410-purwa_camss-v1-0-eedcf6d9d8ee@oss.qualcomm.com> <20260410-purwa_camss-v1-1-eedcf6d9d8ee@oss.qualcomm.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20260410-purwa_camss-v1-1-eedcf6d9d8ee@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/04/2026 05:25, Wenmeng Liu wrote: > Add bindings for the Camera Subsystem for X1P42100. > > The X1P42100 platform provides: > - 2 x CSIPHY > - 3 x TPG > - 3 x CSID > - 2 x CSID Lite > - 1 x IFE > - 2 x IFE Lite > > Signed-off-by: Wenmeng Liu > --- > .../bindings/media/qcom,x1p42100-camss.yaml | 424 +++++++++++++++++++++ > 1 file changed, 424 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..8bfa7e616c3b6b91adc8e21ebfbbe6fb579484f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,x1p42100-camss.yaml > @@ -0,0 +1,424 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,x1p42100-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm X1P42100 Camera Subsystem (CAMSS) > + > +maintainers: > + - Wenmeng Liu > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,x1p42100-camss > + > + reg: > + maxItems: 14 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_wrapper > + - const: csiphy0 > + - const: csiphy4 > + - const: csitpg0 > + - const: csitpg1 > + - const: csitpg2 > + - const: vfe0 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + '#address-cells': > + const: 2 > + > + '#size-cells': > + const: 2 > + > + ranges: true > + > + clocks: > + maxItems: 22 > + > + clock-names: > + items: > + - const: camnoc_nrt_axi > + - const: camnoc_rt_axi > + - const: core_ahb > + - const: cpas_ahb > + - const: cpas_fast_ahb > + - const: cpas_vfe0 > + - const: cpas_vfe_lite > + - const: cphy_rx_clk_src > + - const: csid > + - const: csid_csiphy_rx > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 10 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy4 > + - const: vfe0 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + interconnects: > + maxItems: 4 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_mnoc > + - const: sf_mnoc > + - const: sf_icp_mnoc > + > + iommus: > + oneOf: > + - items: > + - description: S1 HLOS IFE and IFE_LITE non-protected read > + - description: S1 HLOS IFE and IFE_LITE non-protected write > + - description: S1 HLOS SFE non-protected read > + - description: S1 HLOS SFE non-protected write > + - description: S1 HLOS CDM IFE non-protected > + - description: Legacy slot 0 - do not use > + - description: Legacy slot 1 - do not use > + - description: Legacy slot 2 - do not use > + - items: > + - description: S1 HLOS IFE and IFE_LITE non-protected read > + - description: S1 HLOS IFE and IFE_LITE non-protected write > + - description: S1 HLOS SFE non-protected read > + - description: S1 HLOS SFE non-protected write > + - description: S1 HLOS CDM IFE non-protected > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: ife0 > + - const: top > + > + vdd-csiphy-0p8-supply: > + description: > + 0.8V supply to a PHY. > + > + vdd-csiphy-1p2-supply: > + description: > + 1.2V supply to a PHY. > + > + phys: > + maxItems: 2 > + > + phy-names: > + items: > + - const: csiphy0 > + - const: csiphy4 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. Supports either standard single sensor mode or > + Qualcomm's combo mode with one sensor in 2x1 + 1x1 data-lane, clock-lane mode. > + > + patternProperties: > + "^port@[0-3]$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint@0: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + description: > + Endpoint for receiving a single sensor input (or first leg of combo). > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 # Base max allows 4 (for D-PHY) > + > + clock-lanes: > + maxItems: 1 > + > + bus-type: > + enum: > + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY > + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY > + > + endpoint@1: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + description: > + Endpoint for receiving the second leg of a combo sensor input. > + > + properties: > + data-lanes: > + maxItems: 1 > + > + clock-lanes: > + maxItems: 1 > + > + bus-type: > + const: 4 # Combo is D-PHY specific > + > + required: > + - data-lanes > + > + allOf: > + # Case 1: Combo Mode (endpoint@1 is present) > + # If endpoint@1 exists, we restrict endpoint@0 to 2 lanes (D-PHY split) > + - if: > + required: > + - endpoint@1 > + then: > + properties: > + endpoint@0: > + properties: > + data-lanes: > + minItems: 2 > + maxItems: 2 > + bus-type: > + const: 4 > + endpoint@1: > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 1 > + bus-type: > + const: 4 > + > + # Case 2: Single Mode (endpoint@1 is missing) > + # We explicitly allow up to 4 lanes here to cover the D-PHY use case. > + - if: > + not: > + required: > + - endpoint@1 > + then: > + properties: > + endpoint@0: > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > +patternProperties: > + "^phy@[0-9a-f]+$": > + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml > + unevaluatedProperties: false > + > + "^opp-table(-.*)?$": > + type: object > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interrupts > + - interrupt-names > + - interconnects > + - interconnect-names > + - iommus > + - power-domains > + - power-domain-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: isp@acb7000 { > + compatible = "qcom,x1p42100-camss"; > + > + reg = <0 0x0acb7000 0 0x2000>, > + <0 0x0acb9000 0 0x2000>, > + <0 0x0acbb000 0 0x2000>, > + <0 0x0acc6000 0 0x1000>, > + <0 0x0acca000 0 0x1000>, > + <0 0x0acb6000 0 0x1000>, > + <0 0x0ace4000 0 0x1000>, > + <0 0x0acec000 0 0x4000>, > + <0 0x0acf6000 0 0x1000>, > + <0 0x0acf7000 0 0x1000>, > + <0 0x0acf8000 0 0x1000>, > + <0 0x0ac62000 0 0x4000>, Is this the full extent of the VFE ? It looks like not to me. For each register block please make sure you cover the _entire_ range of the block not just the RDI part of it. > + <0 0x0acc7000 0 0x2000>, > + <0 0x0accb000 0 0x2000>; > + > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csid_wrapper", > + "csiphy0", > + "csiphy4", > + "csitpg0", > + "csitpg1", > + "csitpg2", > + "vfe0", > + "vfe_lite0", > + "vfe_lite1"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, _SRC clocks are generally not necessary, is this one ? > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + > + clock-names = "camnoc_nrt_axi", > + "camnoc_rt_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe_lite", > + "cphy_rx_clk_src", > + "csid", > + "csid_csiphy_rx", > + "csiphy0", > + "csiphy0_timer", > + "csiphy4", > + "csiphy4_timer", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy4", > + "vfe0", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + > + interconnect-names = "ahb", > + "hf_mnoc", > + "sf_mnoc", > + "sf_icp_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x60>, > + <&apps_smmu 0x820 0x60>, > + <&apps_smmu 0x840 0x60>, > + <&apps_smmu 0x860 0x60>, > + <&apps_smmu 0x18a0 0x0>; Please define which IOMMUs these are - I'd like to make sure the top level node maps the IFE IOMMUs and not the ICP IOMMUs - as ICP should be its own sub/separate node. > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + power-domain-names = "ife0", > + "top"; > + > + vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; > + vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + csiphy_ep0: endpoint { > + data-lanes = <0 1>; > + remote-endpoint = <&sensor_ep>; > + }; > + }; > + }; > + }; > + }; >